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Start Over You searched for: Degree PHD Remove constraint Degree: PHD Committee Member Vijaykrishnan Narayanan Remove constraint Committee Member: Vijaykrishnan Narayanan

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1. Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems

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Open Access

2. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors

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3. Exploring Power Reliability Tradeoffs in On-Chip Networks

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4. Redundancy and Parallelism Tradeoffs for Reliable, High-Performance Architectures

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5. Implications of Future Technologies on the Design of FPGAs

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6. RELIABILITY ANALYSIS AND OPTIMIZATION FOR NANOSCALE SYSTEM-ON-CHIP DESIGN

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7. Issues in low-power and reliable wireless commuication system design

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8. Network-on-Chip Architectures: A Holistic Design Exploration

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9. SOFT ERROR RATE SIMULATION AND INITIAL DESIGN CONSIDERATIONS OF NEUTRON INTERCEPTING SILICON CHIP (NISC)

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10. FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS

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11. Clock Network and Phase-Locked Loop Power Estimation and Experimentation

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12. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures

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13. Sensor Network Interoperability and Reconfiguration through Mobile Agents

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14. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS

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17. EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES

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18. Energy-aware hardware and software optimizations for embedded systems

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19. System Level Power and Reliability Modeling

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20. HIGH-PERFORMANCE SIGNAL PROCESSING ON RECONFIGURABLE PLATFORMS

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21. A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems

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22. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications

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23. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY

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25. A Configurable Platform for Sensor and Image Processing

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26. Quality of Service Provisioning in Clusters

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27. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS

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28. Secure Communications in Sensor Networks

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29. DEVELOPMENT OF AN ION TIME-OF-FLIGHT SPECTROMETER FOR NEUTRON DEPTH PROFILING

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30. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS

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31. Addressing Reliability Issues in Performance-Critical Processor Structures

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32. Accessing Spatial Information in Resource-constrained and Resource-rich Environments

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33. A Reliable Design Flow for Platform FPGAs.

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34. Application-Aware On-Chip Networks

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35. Analysis of Failures in Nanoscale Devices

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36. SOFT ERRORS IN LOGIC CIRCUITS: ANALYSIS AND MODELING

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37. Influence of Emerging Technologies on Interconnect Architectures

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40. Power Management of Enterprise Storage Systems

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41. CLOSING THE GAP BETWEEN FPGAs AND ASICs: THE APPLICATIONS OF CLOCK SKEW SCHEDULING ON FPGAs

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42. EMBEDDED HARDWARE FACE DETECTION FOR DIGITAL SURVEILLANCE SYSTEMS

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44. DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES

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46. ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION

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48. Design Exploration for Three-dimensional Integrated Circuits (3DICs)

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49. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs

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50. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS

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51. Mobile Agent-Based Energy-Efficient and Secure Global Information Systems

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53. Domain-specific Accelerators on Reconfigurable Platforms

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54. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors

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55. Design Fabrication and Characterization of Antimonide MOS Transistors

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56. Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems

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57. Accelerating Design and Implementation of Embedded Vision Systems

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58. Tracing footprints of Environmental events in tree ring chemistry using Neutron Activation Analysis

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59. Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications

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60. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity

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61. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System

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62. system-on-chip integration of heterogeneous accelerators for perceptual computing

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63. Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications

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64. A Study of DRAM Optimization to Break the Memory Wall

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65. Rethinking the memory hierarchy design with nonvolatile memory technologies

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66. Configurable Accelerators for Visual and Text Analytics

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67. using attention to enhance efficiency in video-based computer systems

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68. An examination of Post-CMOS computing techniques using steep-slope device-based architectures

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69. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory

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70. Device Circuit Interactions for Steep Switching Slope Devices

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71. design methodologies of three-dimensional integrated circuits (3D ICs)

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72. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline

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73. Architecting Byte-addressable Non-volatile Memories for Main Memory

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74. Three Dimensional Integrated Circuit Design and Test

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75. Variation Study on Advanced Cmos Systems for Low Voltage Applications

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76. Large-Scale Object Recognition for Embedded Wearable Platforms

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77. COMPLIMENTARY III-V HETERO-JUNCTION TUNNEL TRANSISTORS FOR ENERGY EFFICIENT NANOELECTRONICS

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78. EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS

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79. DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS

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80. DATA DEPENDENT OPTIMIZATION VISION ARCHITECTURE

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81. Design and Exploration of Accelerator-rich Multi-core Systems

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82. Enabling New Computation Paradigms with Emerging Technologies

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83. Self-powered Internet-of-Things Nonvolatile Processor and System Exploration and Optimization

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84. ENERGY-EFFICIENT AND SECURE DESIGNS OF SPINTRONIC MEMORY: TECHNIQUES AND APPLICATIONS

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85. Context-Aware Design and Optimization of Embedded Deep Neural Network Architectures

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86. Domain Enriched Learning for Brain Image Analysis

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87. MONOLITHIC-3D (M3D) INTEGRATION BASED ROBUST IN-MEMORY COMPUTING SYSTEMS

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88. Data Reduction for Communication-efficient Machine Learning

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89. Design of a Vision Based Assistive System for Visually Impaired Persons

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90. DESIGN OF PROCESSING-IN-MEMORY ARCHITECTURES FOR DEEP LEARNING AND GRAPH APPLICATIONS

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91. Video Analytics with In-SSD Processing Approaches

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92. Efficient Deep Neural Networks Architectures for Video Analytics Systems

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93. Effective and Pleasant Interactive Dialog System Design for Guiding People with Visual Impairments

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94. Stacked-3D and Processing-in-memory Solutions for Data-intensive and Persistent Applications

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95. Optimizing Deep Learning for Memory and Compute : A joint Algorithm-Architecture Exploration

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96. Technology Driven Architecture Support for Memory Hierarchies

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97. Embedded biomedical systems for assistive technology and state-of-vigilance forecasting

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98. Efficiently supporting and exploiting multiple concurrent views of data in the memory hierarchy

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99. Context-Aware Perception for Edge and Embedded Devices

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100. Automatic Recognition of Birdsong Syllables Using Ultra-Sparse Spike Sequence Representations

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