1. Clock Network and Phase-Locked Loop Power Estimation and Experimentation Open Access Author: Duarte, David Enrique Title: Clock Network and Phase-Locked Loop Power Estimation and Experimentation Graduate Program: Electrical Engineering Keywords: CPU clock energy modelingpower estimationPLL designlow power VLSI design File: Download thesis.pdf Committee Members: William Evan Higgins, Committee MemberKenneth Jenkins, Committee Chair/Co-ChairMary Jane Irwin, Committee Chair/Co-ChairVijaykrishnan Narayanan, Committee MemberThomas Nelson Jackson, Committee Member
