Open Access
Cheng, Hsiang-Yun
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
May 27, 2016
Committee Members:
  • Mary Jane Irwin, Dissertation Advisor
  • Mary Jane Irwin, Committee Chair
  • John Morgan Sampson, Committee Member
  • Vijaykrishnan Narayanan, Committee Member
  • Kenneth Jenkins, Outside Member
  • Memory systems
  • Asymmetric access
  • Energy efficiency
  • Cache
  • Memory request scheduling
  • Power management
  • Non-volatile memory
The memory hierarchy, including on-chip caches and off-chip main memory, is becoming the performance and energy bottleneck in multi-core systems, and architectural techniques are needed to tackle the challenge. With the increasing number of cores in multi-core systems, abundant data accesses from variant applications contend for the limited memory resources, such as cache capacity and memory bandwidth, provided by traditional memory systems. Moreover, the power consumption of memory systems has become an important design constraint in performance scaling at the coming dark silicon era. As a result, computer architects are facing significant challenges in designing high performance and energy-efficient memory systems. Emerging memory technologies, such as nonvolatile memories (NVMs), introduce new opportunities to tackle the challenge by exploiting their high density, low leakage, and non-volatile features. Nevertheless, architectural approaches are required to alleviate the disadvantage of high write latency and energy in NVMs. To address the performance and energy challenges in multi-core memory systems, this dissertation designs efficient memory management policies through exploiting and accommodating asymmetries in memory. Variant types of asymmetries in memory are explored, including asymmetric read-write access semantics, asymmetric access pattern, and asymmetric memory technologies. By exploiting and accommodating different types of asymmetries in memory, three solutions are proposed to improve the performance and energy efficiency of multi-core systems with the memory hierarchy built by conventional SRAM/DRAM, emerging NVMs, or hybrid technologies. First, this dissertation studies asymmetric read-write access semantics and proposes a write-aware memory request scheduling policy to improve performance through mitigating write-induced interference. Although reads are usually prioritized over writes in the memory controller, writes eventually need to be serviced when the write queue is full. Servicing a higher number of writes in a burst can reduce the bus turnaround penalty and increase the row-buffer hit rate by exposing more writes together. However, the queuing latency of reads also increases. This dissertation analyzes the pros and cons of servicing a long burst of writes, and proposes a run-time mechanism to schedule reads and writes according to the workload behavior. By considering the impact of row-buffer locality and queuing delay, the proposed scheduling policy provides significant performance improvement in multi-core systems with DRAM-based and NVM-based main memory. Second, this dissertation exploits the asymmetric access pattern among different portions of last-level caches (LLCs) and presents a low-overhead mechanism to reduce the power consumption of SRAM-based LLCs. Power management for LLCs is important in multi-core systems, as the leakage power of LLCs accounts for a significant fraction of the limited on-chip power budget. Since not all workloads running on multi-core systems need the entire cache, portions of a large, shared LLC can be disabled to save energy. This dissertation explores different design choices, from circuit-level cache organization to architectural management policies, to propose a low-overhead mechanism for energy reduction. Based on the extensive experimental analysis, this dissertation finds that simultaneously exploiting three key types of access pattern, i.e, utilization, hotness, and the distribution of dirty cache lines, is necessary to design the power management policies for an energy-efficient LLC. Finally, a novel selective inclusion policy for NVM-based LLCs with asymmetric read-write energy is introduced to improve the energy efficiency. In NVM-based LLCs, dynamic energy from write operations can be responsible for a larger fraction of total cache energy than leakage. This property leads to the fact that no single traditional inclusion policy being dominant in terms of LLC energy consumption for LLCs with asymmetric read-write energy. Based on this observation, a novel inclusion policy is proposed to incorporate advantages from both non-inclusive and exclusive designs. In order to reduce redundant writes and energy consumption, the proposed policy selectively caches the frequently reused clean data in particular levels of the cache hierarchy. Furthermore, a variant of the selective inclusion policy is developed to illustrate that the detection of frequently reused clean data can help to achieve more energy-efficient data placement in hybrid SRAM/NVM LLCs.