design methodologies of three-dimensional integrated circuits (3D ICs)

Open Access
Zou, Qiaosha
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
March 02, 2015
Committee Members:
  • Yuan Xie, Mary Jane Irwin, Dissertation Advisor
  • Yuan Xie, Committee Chair
  • Mary Jane Irwin, Committee Chair
  • Vijaykrishnan Narayanan, Committee Member
  • Donghai Wang, Committee Member
  • Integrated circuits
  • design methodologies
  • three-dimensional circuits
  • cost-aware designs
  • reliability-aware designs
The continuous technology scaling results in the growing delay gap between transistors and interconnects because of the significant increase inparasitics. Moreover, the increased integration density and design complexity exacerbate the interconnect issue from both the rising routing requirements and the prolong wirelength. Recently, the emerging three-dimensional integrated circuits (3D ICs) have been studied intensively as one potential solution towards the future high performance and energy efficient computing systems. Different from previous system-in-package (SiP) designs that stack multiple chips and use wires or bumps for connections, the emerging 3D integration provides finer granularity integration thanks to the vertical interconnects inside chips. In general, 3D ICs provide numerous advantages over traditional 2D IC designs, such as smaller footprint, high bandwidth and short latency interconnects, and the capability of heterogeneous stacking. Nevertheless, there are several challenges in 3D ICs that need to be solved before this technology is applied in commercial designs with high volume production, such as higher fabrication cost, compromised system reliability, the lack of mature electrical design automation tools, the elevated chip operation temperature, and the insufficient understanding on chip testings. The relatively complicate fabrication process implicates higher cost of 3D ICs compared to 2D counterparts. As the cost is the primary driving force for the new technology adoption, reducing the system cost becomes the one of the primary concerns in 3D designs. On the other hand, the success of this emerging technology should be guaranteed by its functionality correctness. However, a few factors influence the 3D reliability: fabrication limitations, thermal mechanical stresses, interconnect electrical failures, degraded signal integrity, and IR droop in power networks. As a result, these factors should be considered and properly addressed in 3D designs to ensure the chip reliability. This dissertation proposes novel design methodologies to optimize 3D designs emphasizing the challenges of cost and reliability. In the first part, a cost model is adapted and applied in our analysis framework to evaluate the 3D system cost. Then cost-aware design methods are proposed to reduce the cost from fabrication level to chip design level. The second part of this dissertation handles the chip reliability problems. Three studies are introduced from diverse aspects to manage the interconnect electromigration, thermal mechanical stresses, and the signal integrity issues.