Influence of Emerging Technologies on Interconnect Architectures

Open Access
Eachempati, Soumya Siva
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
June 08, 2010
Committee Members:
  • Vijaykrishnan Narayanan, Dissertation Advisor
  • Vijaykrishnan Narayanan, Committee Chair
  • Yuan Xie, Committee Chair
  • Chitaranjan Das, Committee Member
  • Mary Jane Irwin, Committee Member
  • Suman Datta, Committee Member
  • Heng Xu, Committee Member
  • carbon nanotube
  • radio frequency
  • FPGA
  • network on chip
ITRS Roadmap of 2001 highlighted the key problems with copper as the increase in conductor resistivity as a consequence of line-widths approaching electron mean free path, electromigration and stress. As a consequence of scaling, electron scattering both at grain and interface boundaries results in higher resistivity. This is posing a problem for copper interconnect even in the near term. Researchers are studying interconnect alternatives ranging over the time line. It is important to understand the total system concept of performance, area, power, reliability, and process variability for each of these alternatives. The goal of this dissertation is to analyze an emerging technology alternative from a system perspective and tune the architecture to fully harness the benefits provided by the new interconnect technology. We study three emerging interconnect technologies namely bundles of Single Walled Carbon Nanotube (SWCNT), Radio frequency (RF-I) and three dimensional (3D) die stacking. SWCNT are shown to possess high electrical and thermal conductivity and thus is envisioned as a possible replacement for copper interconnect in the far-term. We apply SWCNT to interconnect dominated FPGA platform and explore the routing fabric design space to leverage the benefits provided by SWCNT. We find that SWCNT prefers longer length segments and lesser number of contacts when area and performance are chosen as the key metrics for comparison. SWCNT are expected to have high process variability and when timing yield of the FPGA was also considered for comparison, smaller length segments were preferred. Thus, reliability and performance trade-offs are studied. Since SWCNT gives more delay benefit for long lengths, we also use it in clock networks and demonstrate significant power and area benefits. Due to the power budget constraints, System-on-Chip (SoC) and multicore systems have also emerged to be communication-oriented. Packet based on chip interconnection networks are being used as the communication media. Network latency, throughput and power will play a vital role in system design. RF-I can provide high bandwidth at small latency across the length of the chip. We study the impact of applying RF-I for various topologies and traffic workloads. At small network sizes, RF-I yields both latency and throughput benefits and at larger network sizes latency benefits are observed. The throughput benefits diminish at the larger network sizes as the congestion over long distances close to saturation increases the probability of deadlocks for a flat topology. During deadlock recovery, RF bandwidth is not used and without the extra BW support at the high load rates the network quickly saturates. On the other hand, concentrated and hierarchical topologies lead to smaller network diameter. Consequently, these topologies can take better advantage of RF-I. In addition, hierarchical designs are throughput constrained and thus, it can benefit from the high BW of the RF-I. Following this, we consider three dimensional stacking that is envisioned to play a critical role in the design of SoC and multicore systems. We designed a 3D multilayered router for on-chip networks that is motivated by the observation that Non-uniform cache (NUCA) communication traffic has many short flits and frequent patterns. Consequently, we can shut off the bottom layers to save power. Novel technologies open up a lot of opportunities and architectural challenges. These studies show that it is essential to design the system architecture ahead of time of the technology and characterize the system with respect to various design metrics. The technology assumptions should be broad enough to take into account the changes in the emerging technology.