Analysis of Failures in Nanoscale Devices
Open Access
- Author:
- Krishnan, Ramakrishnan
- Graduate Program:
- Electrical Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- October 22, 2009
- Committee Members:
- Vijaykrishnan Narayanan, Dissertation Advisor/Co-Advisor
Vijaykrishnan Narayanan, Committee Chair/Co-Chair
Suman Datta, Committee Chair/Co-Chair
Dr Yuan Xie, Committee Member
Mary Jane Irwin, Committee Member
Kenan Unlu, Committee Member
Ram Mohan Narayanan, Committee Member
Kenneth Jenkins, Committee Member - Keywords:
- Reliability
- Abstract:
- Aggressive downscaling of transistor sizes for increased performance and lower costs have pushed the devices to their physical limits. Design goals are governed by several factors other than power, performance and area such as variations and reliability margins. The reliability of a system is affected from it’s birth to death by various phenomena such as process variations, soft and hard faults and aging mechanisms. Reliability effects have also become a major bottleneck due to dif- ferent physical phenomena and introduction of newer materials. Process variation poses a huge threat to the reliability of the system during the initial days of chip operation. Various transient mechanisms such as radiation induced soft errors and cross talk alter system operation during the useful lifetime of a chip. In the near end of it’s lifetime, several aging phenomena such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) limit the frequency of opera- tion. Soft errors and NBTI are two major reliability threats that require detailed analysis and methods to ensure high reliability limits. Accelerated testing mech- anisms, fast and accurate CAD tools to estimate the impact of failures and good design techniques are required for designers to promise high margins of reliabil- ity. These necessities along with the interaction of the reliability phenomena with concerns such as variations have been addressed comprehensively. Tool for faster and accurate calculation of Soft Error Rate (SER) of hierarchical structures called Hierarchical Soft Error Estimation Tool (HSEET) have been developed. A frame- work called New-Age for estimation of degradation caused due to NBTI has also been developed for complete system analysis. Analysis of the interplay of varia- tions with the SERs have been performed. FPGAs which have become a highly popular architectures due to its reconfigurability are also susceptible to these re- liability dangers. We also show the impact of NBTI on FPGAs and proposed solutions to increase its lifetime. The impact of NBTI on sequential circuits have been performed.