Three Dimensional Integrated Circuit Design and Test

Open Access
Author:
Xie, Jing
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
March 20, 2015
Committee Members:
  • Yuan Xie, Dissertation Advisor
  • Mary Jane Irwin, Dissertation Advisor
  • Vijaykrishnan Narayanan, Committee Member
  • Zhiwen Liu, Committee Member
  • Lee David Coraor, Committee Member
Keywords:
  • VLSI
  • Three Dimensional Integrated Circuit
  • Testing
  • Circuit Design
  • Low Power
  • High Performance
Abstract:
The emerging three-dimensional integrated circuits (3D ICs) is one of the most promising solutions for future IC designs. 3D stacking enables much higher memory bandwidth and much lower overhead in multi-power domain design, which provides solutions for chip-multiprocessor design in mitigating the "memory wall" and "dark-silicon" problem. At the same time, 3D technology leads to new opportunities and challenges in the field of circuit and system design techniques, EDA tools and chip testing mechanism. This dissertation presents two killer applications for the modern 3D system and one 3D testing solution. The first contribution of this dissertation is to propose a killer application for TSV based system - the 3D memory stacking. This dissertation presents a 3D memory stacking system that leverages the massive number of TSVs between memory layers to help high-bandwidth checkpointing/restore. To validate the proposed scheme, 2-layer TSV-based SRAM-SRAM 3D-stacked chip is implemented to mimic the high-bandwidth and fast data transfer from one memory layer to another memory layer, so that the in-memory checkpointing/restore scheme can be enabled for the future exascale computing. The capacity of each SRAM layer is 1 Mbit. Each layer contains 64 banks, with each bank contains 256 words and the word length is 64-bit. The final footprint including I/O pad is 2.9mm X 2mm. The SRAM dies were taped out in GlobalFoundries using its 130nm low power process, and the 3D stacking was done by using Tezzaron's TSV technology. The prototyping chip can perform checkpointing/restore at the speed of 4K/cycle with 1Ghz clock. This dissertation also gives an applicable solution for 3D testing. Testing for 3D ICs based on through-silicon-via (TSV) is one of the major challenges for improving the system yield and reducing the overall cost. The lack of pads on most tiers and the mechanical vulnerability of tiers after wafer thinning make it difficult to perform 3D Known-Good-Die (KGD) test with the existing 2D IC probing methods. This dissertation presents a novel and time-efficient 3D testing flow. In this Known-Good-Stack (KGS) flow, a yield-aware TSV defect searching and replacing strategy is introduced. The Build-in-Self-Test (BIST) design with TSV redundancy scheme help improve the system yield for today's imperfect TSV fabrication process. Our study shows that less than 6 redundant TSVs is enough to increase the TSV yield to 98% for a TSV cluster with a size under 16 X 16 with relatively low initial TSV yield. The average TSV cluster testing and self-fixing time is about 3-16 testing cycle depending on the initial TSV yield. The second killer application for 3D system in this dissertation is multi-power domain system design utilizing the monolithic technology. Optimizing energy consumption for electronic systems has been an important design consideration. Among all the techniques, multi-power domain design is a widely used one for low power and high performance applications. In order to perform the data transfer between these different power domains, we needs a cross power domain interface (CPDI). The existing level-conversion flip-flop (LCFF) structures all require dual power rails, which results in large area and performance overhead. We proposed a scan-able CPDI circuit utilizing monolithic 3D technology. This interface functions as a flip-flop and provides reliable data conversion from one power domain to another. It also has built-in scan feature which makes it testable. Our design separates power rails in each tier, substantially reduced physical design complexity and area penalty. The design is implemented in a 20nm, 28nm and 45nm low power technology. It shows 20%-35% smaller D to Q comparing with normal designs. The proposed design also shows scalability and better energy consumption than precious LCFF design. Finally, we presented a dual power domain deep pipeline circuit architecture for future power-efficient systems. We reduce the power consumption by putting all the combinational logics in a lower power domain, while all the FFs and clock network operate at normal voltage for smaller insertion delay and better clock control. In order to realize these functions and system benefits, we proposed a novel level conversion flip flop omega design, which has 30% insertion delay than the normal flop design and could be easily integrated into today’s synthesis flow. This work provides guideline on how to design a dual power domain system with less power under the same system throughput requirement. A system level estimation shows that the 3D dual power supply system could consume about 15% less energy by using our design methodology.