An examination of Post-CMOS computing techniques using steep-slope device-based architectures

Open Access
Author:
Swaminathan, Karthik Venkataraman
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
August 27, 2014
Committee Members:
  • Vijaykrishnan Narayanan, Dissertation Advisor
  • Mahmut Taylan Kandemir, Committee Member
  • Anand Sivasubramaniam, Committee Member
  • Jack Sampson, Committee Member
  • M Jeya Chandra, Committee Member
Keywords:
  • Beyond-CMOS computing
  • Heterojunction Tunnel FET (TFET)
  • device-to-architecture abstraction
  • heterogeneous architectures
Abstract:
As technology scaling results in smaller and smaller transistor sizes, existing CMOS technology starts to encounter certain fundamental physical limitations. These limitations can potentially result in drastic reduction in performance and energy efficiencies of these transistors, which could make it untenable to continue scaling them. This in turn, would severely limit the benefits of further innovations in processor design and architecture. In this scenario, there have been several alternatives proposed at the device level. However, each of these devices comes with varying energy-performance tradeoffs and optimal design points in comparison to CMOS technology. Hence, there is a need for a rethink of the complete design hierarchy, ranging from a simple circuit to entire processor platforms. In my work, I attempt to answer the question, Does a better device make a better processor?, by examining the impact of varying device parameters at the architecture-level. I carry out a comprehensive exploration of different design points, at the micro-architecture and architecture levels of abstraction and examine the feasibility of deviceheterogeneous architectures for achieving greater regions of optimality. My work also extends to gauging the impact of using these emerging technologies on non-traditional architectures, including domain specific accelerators and 3D-stacked processors.