Classical And Coulomb Blockade Iii-v Multi-gate Quantum Well Field Effect Transistors For Ultra Low Power Logic Applications

Open Access
Liu, Lu
Graduate Program:
Electrical Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
November 20, 2013
Committee Members:
  • Suman Datta, Dissertation Advisor
  • Suman Datta, Committee Chair
  • Theresa Stellwag Mayer, Committee Member
  • Vijaykrishnan Narayanan, Committee Member
  • Jerzy Ruzyllo, Committee Member
  • Nitin Samarth, Committee Member
  • multi-gate
  • quantum well FET
  • single electron
  • Coulomb blockade
  • non-volatile
  • low power
Low power logic application requires aggressive scaling of supply voltage while maintaining performance. Recently, III-V material systems such as InGaAs and InSb have attracted lots of research interest as a substitute for silicon for future semiconductor industry. The In0.7Ga0.3As quantum well system is a good n-channel candidate for sub-500mV low power logic application due to their superior electron mobility. On the other hand, aggressive device scaling, into few electron operation regime, provides new opportunity to explore Coulomb oscillation to implement logic in a suitable binary decision diagram (BDD) logic architectur, enabling sub-300mV logic application. This dissertation focuses on the experimental design, fabrication and characterization of classical and Coulomb blockade multi-gate quantum well field effect transistor (MuQFET), as well as the lead zirconium titanate ferroelectric integration to realize non-volatile operation. Based on comprehensive understanding of measurement results and device modeling, the following key accomplishments are discussed: (1) quasi-ballistic transport in short channel In0.7Ga0.3As MuQFETs; (2) multi-functional programmable MuQFETs showing short, Coulomb blockade and open mode for reconfigurable BDD logic in the few electron regime near scaling limit; (3) non-volatile ferroelectric gate stack exhibiting more than 40 minutes retention for short, Coulomb blockade and open mode. These features provide the opportunity of implementing low power logic using reconfigurable non-volatile BDD hexagonal fabrics combining with appropriate sensing circuit between BDD stages.