RELIABILITY ANALYSIS AND OPTIMIZATION FOR NANOSCALE SYSTEM-ON-CHIP DESIGN

Open Access
Author:
Vaidyanathan, Balaji
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
December 09, 2009
Committee Members:
  • Yuan Xie, Dissertation Advisor
  • Yuan Xie, Committee Chair
  • Vijaykrishnan Narayanan, Committee Member
  • Mary Jane Irwin, Committee Member
  • Heng Xu, Committee Member
  • Anthony S Oates, Committee Member
  • Raj Acharya, Committee Member
Keywords:
  • circuit reliability
  • system-on-chip
Abstract:
System-on-Chip occupies a major share of electronic market with products ranging from consumer electronics like cellphone, iPod, gaming machines, PDA, netbooks, smartbooks, and safety critical applications like medical and military electronics. Technology scaling is an important driver in obtaining a highly integrable and compact version of these commodity products. However, the scaling beyond 45nm has brought with it plethora of issues like process variation, progressive aging, di-electric breakdown mechanisms, radiation sensitivity, crosstalk, among many others. From the functionality perspective SoC can be sub-divided into logic, memory, analog/RF and system bus. Each of the sub-component have distinct functions and different reliability metrics that guide their qualification. In this thesis we model the reliability mechanisms covering NBTI, HCE, SER, crosstalk; analyze and predict their impact on the SoC sub-components. Using the gained insight, we propose solutions at circuit level to overcome them. Specifically in Chapter 2 we outline a silicon verified statistical aging prediction tool that helps in tracking two important phenomenons namely, aging and process variation. In Chapter 3, we analyze pipeline logic statistical aging and propose solutions to buy back the lost yield during its operational lifetime. Subsequently we also analyze hardening techniques for asynchronous control circuitry comprising of C-elements against radiation induced soft errors. In chapter 4 we propose a novel heterogeneous 3D architecture for on-chip caches to collectively reduce statistical aging induced lifetime yield effects and also the manufacturing cost. A silicon verified compact analytical model for alpha and neutron SER prediction is proposed that is used to predict the eDRAM versus SRAM SER trend for the next generation technology. In Chapter 5 we analyze aging in on-chip bus and propose a novel hardware based runtime adaptive technique to allow system bus functionality to gracefully degrade with aging. Additionally we analyze crosstalk induced power consumption in on-chip buses and propose an add-on algorithm to the existent code compression scheme to reduce the same without any power, performance, or area overhead.