Designing Cool Chips: Low Power and Thermal-Aware Design Methodologies

Open Access
Hung, Wei-Lun
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
September 25, 2006
Committee Members:
  • Yuan Xie, Committee Chair
  • Mary Jane Irwin, Committee Member
  • Zhiwen Liu, Committee Member
  • Vijaykrishnan Narayanan, Committee Member
  • placement
  • algorithm
  • VLSI
  • CAD
  • thermal
  • EDA
  • floorplanning
Power is one of the rigid challenges for high performance computer system designs and for the widespread use of portable and wireless electronic systems. With technology continuing to scale down, the power issue is even more prominent than before, with the highly integration capability on a single chip. Power dissipation affects battery life and performance, and greatly affects reliability and cooling costs. Thus, reducing power consumption has become more and more important in the nanometer era. With the power issues induced from technology scaling, temperature in modern high performance VLSI circuits has moved up dramatically due to smaller feature sizes, higher packing densities, and rising power consumptions. Temperature affects not only the reliability but also the performance, power, and cost of the chip designs. Power-aware design alone is not able to address the temperature challenge. Thus, both low power and thermal-aware techniques need to be adopted jointly to combat the ever-increasing power and thermal related problems. One power optimization framework based on the genetic algorithm has been proposed. The optimization strategy can simultaneously perform multiple-Vdd assignment, multiple-Vth assignment, and gate sizing in conjunction with stacking force techniques to minimize total power consumption, while maintaining performance requirements. The effectiveness of the proposed total power optimization framework was validated by conducting various experiments. A thermal-aware floorplanner is advocated to reduce the hot spot temperatures for two-dimensional chips and is further enhanced to tackle the thermal issues of three-dimensional integrated circuits. The uniqueness of the proposed floorplanner is that it accounts for the effects of the interconnect power consumption in estimating the peak temperature, while still maintaining good traditional floorplanning design metrics. The thermal-aware floorplanner is then applied to System-on-Chip designs to combat the voltage island partitioning and floorplanning problems. A thermal-aware task allocation and scheduling algorithm is also proposed for embedded systems. The algorithm is used as a sub-routine for hardware/software co-synthesis to reduce the peak temperatures and to achieve a thermally balanced system. Finally, a thermal-aware IP placement algorithm is proposed for Networks-on-Chip architecture. Since the temperature distribution profile of the chip depends on the IP core virtualization and placement, the algorithm is able to alleviate the thermal issues by taking this factor into consideration. The proposed framework can not only reduce the hot spot temperature, but can also minimize the communication cost through placement, which results better performance.