VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS

Open Access
Author:
Chen, Yibo
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
August 22, 2011
Committee Members:
  • Yuan Xie, Dissertation Advisor
  • Yuan Xie, Committee Chair
  • Vijaykrishnan Narayanan, Committee Member
  • Sencun Zhu, Committee Member
  • Suman Datta, Committee Member
Keywords:
  • High-Level Synthesis
  • Behavioral Synthesis
  • ESL
Abstract:
Variability in circuit delay and power dissipation is one of the most critical challenges in nanometer VLSI era. Traditionally, performance/power variations are handled by a combination of speed/power binning and design margining. However, these solutions are becoming insufficient as the variability increases along with technology scaling, and may not be a viable solution when the variability encountered in the new process technologies becomes very significant. As a result, a shift in the design paradigm, from today's deterministic design to statistical or probabilistic design, is critical for deep sub-micron design. There has been initial exploration on addressing the variability issues in behavioral synthesis, by augmenting existing deterministic synthesis flow to be variation-aware. This thesis extends the current variation-aware behavioral synthesis by 1) improving the behavioral synthesis flow with new optimization techniques; 2) exploring the impact of process variability on conventional module-level optimizations such as using transparent flip-flops and multi-voltage in a single design; 3) exploring new types of circuit variability such as NBTI in behavioral synthesis; 4) combining the mitigation of process variability with the new emerging 3D IC technology. Analysis results indicate these proposed techniques are very effective in tackling the variability issue for nanometer VLSI chips.