ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION

Open Access
Author:
Ye, Wu
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
November 15, 1999
Committee Members:
  • Vijaykrishnan Narayanan, Committee Member
  • Mary Jane Irwin, Committee Chair
  • Dr Ali R Hurson, Committee Member
  • John Joseph Hannan, Committee Member
  • Shizhuo Yin, Committee Member
Keywords:
  • SimplePower
  • Power Estimation
  • RTL
  • Architectural Level Power Estimation/Optimization
  • Partitioning Power Modeling Technique
  • Transition-Sensitive Energy Model
Abstract:
With the emergence of a plethora of embedded and portable applications and ever increasing integration levels, power dissipation of integrated circuits has moved to the forefront as a design constraint. Recent years have also seen a significant trend towards designs starting at the architectural (or RT) level. Those demand accurate yet fast RT level power estimation methodologies and tools. This thesis addresses issues and experiments associate with architectural level power estimation. <br><br> An execution driven, cycle-accurate RT level power simulator, SimplePower, was developed using transition-sensitive energy models. It is based on the architecture of a five-stage pipelined RISC datapath for both 0.35um and 0.8um technology and can execute the integer subset of the instruction set of SimpleScalar. SimplePower measures the energy consumed in the datapath, memory and on-chip buses. During the development of SimplePower, a partitioning power modeling technique was proposed to model the energy consumed in complex functional units. The accuracy of this technique was validated with HSPICE simulation results for a register file and a shifter. <br><br> A novel, selectively gated pipeline register optimization technique was proposed to reduce the datapath energy consumption. It uses the decoded control signals to selectively gate the data fields of the pipeline registers. Simulation results show that this technique can reduce the datapath energy consumption by 18-36% for a set of benchmarks. <br><br> A low-level back-end compiler optimization, register relabeling, was applied to reduce the on-chip instruction cache data bus switch activities. Its impact was evaluated by SimplePower. Results show that it can reduce the energy consumed in the instruction data buses by 3.55-16.90%. <br><br> A quantitative evaluation was conducted for the impact of six state-of-art high-level compilation techniques on both datapath and memory energy consumption. The experimental results provide a valuable insight for designers to develop future power-aware compilation frameworks for embedded systems.