COMPLIMENTARY III-V HETERO-JUNCTION TUNNEL TRANSISTORS FOR ENERGY EFFICIENT NANOELECTRONICS

Open Access
Author:
Pandey, Rahul
Graduate Program:
Electrical Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
June 27, 2016
Committee Members:
  • Suman Datta, Dissertation Advisor
  • Vijaykrishnan Narayanan, Committee Chair
  • Jerzy Ruzyllo, Committee Member
  • Sumeet Gupta, Committee Member
  • Roman Engel-Herbert, Outside Member
Keywords:
  • Tunnel
  • Tunnel Transistor
  • Energy
  • Power
  • Efficient
  • Low-power
  • Energy efficient
  • low voltage
  • TFET
  • MOSFET
  • CMOS
  • Moore's law
  • Transistor
  • on-current
  • steep
  • subthreshold
  • switching
  • sub-thermal
  • logic
  • circuits
  • systems
  • memory
  • semiconductors
  • TunnelFET
  • complimentary
  • III-V
  • compound semiconductors
  • Germanium
  • GeSn
  • Hetero-junctions
  • tunnel barrier engineering
  • quantum mechanical tunneling
Abstract:
As we venture into the era of Internet of Things, we witness a data explosion driven by a network of intelligent electronic devices with multi-modal sensing capabilities. Consequently, there is a significant demand for low-latency high-performance data processing which is not only reliable but also energy efficient. The requirement of maintaining high performance at extremely low power is especially critical for mobile platforms. The silicon MOSFET which is the workhorse of today’s semiconductor industry has addressed this demand through relentless shrinking of its dimensions and steady reductions to its operating voltage. However, the benefits wrought by reducing the size of the transistor, which are detailed in Moore’s law, are now under threat. If the threshold voltage of the silicon MOSFET were reduced to enable a scaling of the operating voltage, there would be an exponential increase in the off-state current and a corresponding explosion in energy loss. This is a prominent concern for circuit designers because the sub-threshold leakage power is as significant as the active power in microprocessors. The high sub-threshold leakage power stems from the inability of the MOSFET to provide steep switching from the on-state to the off-state. This limit has driven efforts to look for alternative devices delivering steeper switching to extend supply voltage scaling without compromising performance. Within this effort, one steep switching device that is piquing the interest of many is the tunnel FET (TFET). In this work, we explore III-V compound semiconductors based GaAs1−xSbx/InyGa1−yAs Hetero-junction Tunnel Field Effect Transistors (HTFETs) for realizing energy-efficient complimentary logic. Both n-channel and p-channel HTFETs are fabricated and characterized, exhibiting best in class on-current and on-off current ratio at |Vds|=0.5V. To further improve the electrical performance of HTFET, we perform an in-depth characterization of critical semiconductor interfaces in HTFET and identify and prescribe metrics for high-performance HTFET design. Moreover, we also investigate HTFET circuit design elements and benchmark its performance against corresponding implementation in sub-threshold Si-FinFET technology. We conclude by presenting a course for enhancing group III-V HTFET technology besides providing a brief insight into potential alternatives for TFET design using group IV semiconductors.