Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity

Open Access
Eze, Melvin
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
October 14, 2013
Committee Members:
  • Vijaykrishnan Narayanan, Dissertation Advisor
  • Vijaykrishnan Narayanan, Committee Chair
  • Mary Jane Irwin, Committee Member
  • Yuan Xie, Committee Member
  • Jerzy Ruzyllo, Special Member
  • Interconnect
  • Signal Integrity
  • Offset Switching
  • Variable Cycle Timing with Temporal Redundancy
  • NBTI
The emergence of System-on-Chip as the dominant chip level architecture in the integrated Circuit industry, has been accompanied by a need to meet the considerable communication requirements of the on-chip processing and I/O blocks. To this end, various commercial vendors have designed and licensed an array of interconnect products such as IBM Core Connect Bus, Altera Avalon, ST Micro ST Bus among others. At the physical level, all these buses are composed of long parallel wire structures that conduct the electrical signals used in communication between on-chip modules. However, with continuing dimension scaling deep below the 0.1 micron threshold, several challenges have emerged to threaten both short term and long term interconnect reliability. In this work, we focus on on-chip buses and explore the effects of basic data transmission on the severity of various phenomena affecting interconnect reliability. Our exploration will span both long and short term interconnect reliability issues such as inter-wire crosstalk, process-induced wire variation and interconnect aging. We will discuss the difficulties inherent in obtaining process-level solutions and propose circuit-level solutions as valid alternatives in many cases. We will propose a tool for profiling bus wire signal transitions in a general purpose processor running benchmark applications, and use the data obtained to generate corresponding bus crosstalk delay profiles, bus variation delay, and bus aging profiles. We will propose circuit techniques to mitigate the effects of these phenomena and compare our solutions to current approaches in the literature.