Open Access
Bae, Sungmin
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
June 07, 2010
Committee Members:
  • Vijaykrishnan Narayanan, Dissertation Advisor
  • Mary Jane Irwin, Committee Member
  • Vijaykrishnan Narayanan, Committee Chair
  • Kyusun Choi, Committee Member
  • Kenan Unlu, Committee Member
  • FPGA
  • clock skew scheduling
  • low power FPGA
  • thermal gradient
  • thermal gradient estimation
Since the first field programmable gate arrays (FPGAs) production in 1985, were used only as glue logic, FPGAs have dramatically improved to compete with application specific integrated circuits (ASICs). Even entire system on chip (SOC) designs can now be built on an FPGA. In addition, today¡¯s trends in shorter life cycles of products, and exponentially increasing costs of the mask and NRE with shrinking process technology make FPGAs the preferred design solutions over ASICs due to the advantages of faster time to market, field reprogrammability, and low non-recurring engineering (NRE) cost. However, the advantages of FPGAs,which have been brought by reconfigurable nature of FPGAs, come with the cost of slower speed, more power, and larger device size. Because FPGAs must use more transistors and interconnects than ASICs for the same functionality. To reduce the performance and power consumption gaps between FPGAs and ASICs, which are limiting factors of further widespread use of FPGAs, FPGA vendors have aggressively adopted the latest process technology with innovative FPGA architectures. Besides the hardware wise optimizations, FPGA CAD (Computer Aided Design) tools also have been improved to have state-of-art ability to optimize logic designs through various stages of the CAD flow. However, even with the optimization efforts, FPGAs are still considered to have 2¡­3 time slower performance and 2¡­5 times more power consumption than ASICs [1]. In this dissertation we propose FPGA architectures and optimization CAD flows utilizing a clock skew scheduling architecture [2] which utilizes timing slacks in the logic designs as a resource for various design optimization goals to reduce the gap further. We first study issues in implementing a clock skew scheduling techniue on an FPGA and possible solutions of the issues, and develop an FPGA architecture and an optimization CAD flow to enhance performance of logic designs implemented on the FPGA by considering some of the issues in the CAD flow. We then develop a low power body biasing FPGA architecture and an optimization CAD flow to enhance power reduction with minimum area overhead by clock skew scheduling technique. Finally, we study a temperature variations adaptable FPGA architecture and an optimization CAD flow utilizing clock skew scheduling technique to minimize performance degradations due to thermal timing margining for operating reliably under harsh environments.