DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS
Open Access
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- August 12, 2016
- Committee Members:
- Vijaykrishnan Narayanan, Dissertation Advisor
- Mary Jane Irwin, Committee Chair
- John Morgan Sampson, Committee Member
- Lee David Coraor, Committee Member
- Sumeet Kumar Gupta, Outside Member
- Keywords:
- Steep Slope Transistor
- Heterojunction Tunnel FETs
- TFETs
- HTFETs
- Digital/Mixed-Signal Circuit Designs
- Energy Efficiency
- Abstract:
- The scaling of silicon complementary metal-oxide-semiconductor (CMOS) has long been the driving force in the improvement of device performance, increase of transistor density, and circuit-energy reduction per operation in modern computing systems. However, the total power consumption has also kept increasing in a scant few nanometer regimes as a number of transistors has increased in modern chips. In order to preserve the same or to even reduce power consumption, a supply voltage (VDD) reduction is essentially desired. However, a VDD scaling has been a challenge due to tradeoffs in improving the device performance and lowering the static off-state (leakage) power dissipation in Si CMOS. In order to further enable a VDD scaling while retaining the same on-state performance at a scaled VDD , the threshold voltage (VTH) has to be reduced proportionally but this VTH scaling leads to severe increase in standby power dissipation because of the fundamental 60mV/decade subthreshold swing (SS) limitation. Hence, this limitation on a VDD scaling impedes the realization of low power and high performance computing systems. In order to mitigate the challenges in a VDD scaling while maintaining low leakage power dissipation, the heterojunction tunnel field-effect transistor (HTFET) has been emerged as a promising transistor candidate for post-CMOS because of its steep SS (i.e., sub-60mV/decade) without compromising on-current. To explore benefits and tradeoffs of HTFETs across a range of circuits, thereby, this dissertation has primarily focused on the co-design framework from the device to circuits in digital/mixed-signal circuit designs. A device-circuit modeling framework is critical to understand the applicability of TFETs across broad application spaces. There is substantial ongoing progress in TFET device development, so such a framework must bridge the different design layers such as device SPICE modeling, circuit implementations, cell library characterization, and architecture benchmarking. In addition, building device-circuit modeling frameworks enables early capture of design insights across a far broader range of applications than an examination at any one of the layers in isolation. In this dissertation, the device-circuit interactions cover the impacts of III-V HTFETs in digital/mixed circuits, stemming from unique device electrical characteristics: a) the steep on-off switching behavior; b) unidirectional conduction; c) asymmetrical source/drain; and d) vertical device structure in a broad range of digital/mixed-signal applications. This dissertation also includes the parasitic extraction, layout analysis, circuit design modifications, and performance metrics examination to explore key insights for steep-slope HTFETs based circuit designs and to examine optimum design spaces by comparing advantages and tradeoffs against baseline Si CMOS designs.