DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS

Open Access
Author:
Wang, Feng
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
March 07, 2008
Committee Members:
  • Yuan Xie, Committee Chair
  • Mary Jane Irwin, Committee Member
  • Vijaykrishnan Narayanan, Committee Member
  • Zhiwen Liu, Committee Member
Keywords:
  • high level synthesis
  • design automation
  • process variations
Abstract:
Technology scaling provides an integration capacity of billions of transistors and continuously enhances system performance. However, fabricating transistors at feature sizes in the deep sub-micron regime is increasingly challenging and leads to significant variations in such critical transistor parameters as transistor channel length, gate-oxide thickness, and threshold voltage. This manufacturing variability consequently causes substantial performance and power deviations from nominal values in identical hardware designs. As technology scales down relentlessly, the impact of these variations becomes even more pronounced. The established practice of designing for the worst case scenario is no longer a viable solution, since it yields overly pessimistic design estimates that unnecessarily increase design and manufacturing costs. This realization has led to a marked shift from deterministic to statistical design methodologies across all levels of the design hierarchy [14]. In this thesis, statistical design techniques ranging from gate level to system level have been proposed to mitigate the impact of the process variations. At the gate level, an efficient method is proposed to compute the criticality for paths and arcs/nodes simultaneously by a single breadth-first graph traversal with linear complexity in circuit size. At the module level, variation aware resource sharing and assignment techniques in high level synthesis is proposed. In addition to the design-time techniques, a module selection algorithm with joint post-silicon tuning and design-time optimization is proposed to further reduce the parametric yield loss. At the system level, the classical task scheduling and allocation algorithm is augmented to be variation aware. Analysis results indicate these proposed techniques are very powerful in tackling the process variability issue.