Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System

Open Access
Niu, Dimin
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
June 13, 2013
Committee Members:
  • Yuan Xie, Dissertation Advisor
  • Vijaykrishnan Narayanan, Committee Chair
  • Mary Jane Irwin, Committee Member
  • Donghai Wang, Committee Member
  • Memory System
  • Non-Volatile Memory
  • Resistive Memory
As leakage power and fabrication difficulty have become major obstacles of DRAM scaling, the search for new technologies as DRAM alternative has gained increased attention. Recently, several emerging non-volatile memory (NVM) technologies, such as Phase Change Random Access Memory (PCRAM or PCM), Spin Torque Transfer Random Access Memory (MRAM or STT-RAM), and Resistive Random Access Memory (ReRAM), have been studied intensively as potential candidates for the next generation memory technologies. Among all of these emerging technologies, ReRAM has been demonstrated with excellent scalability beyond the 10nm technology node, fast speed with <10ns access latency, and capability of high density due to the multi-level cell (MLC) and cross-point array structure. However, there are several challenges before ReRAM can be adopted as a viable commercial main stream technology. First, cell-level non-uniformity, which is caused by the process variation and stochastic switching mechanism of resistance switching materials, requires a worst-case design methodology. The worst-case design results in a significant waste of energy consumption and the degradation of performance. Second, at array-level, although the cross-point structure is effective in improving the memory density, its inherent disadvantages, such as sneak current and voltage drop along metal wires, introduce extra design challenges. Third, as an emerging memory technology, ReRAM-based main memory lacks architecture-level exploration and optimization. This dissertation proposes to model and architect a low cost and high performance ReRAM-based main memory with optimization methods from both circuit-level and architecture-level. First, a mathematical model is built to evaluate reliability, energy consumption, area overhead, and performance for ReRAM at array-level. Second, based on the mathematical model, we conduct a design space exploration and propose an architecture-level ReRAM main memory design. Third, we introduce a design flow and provide key insights into architectural tradeoffs of ReRAM chips among different array structures and cell parameters. In addition, multiple design optimizations are proposed to further improve the performance and energy efficiency of a reliable ReRAM main memory design.