Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures

Open Access
Author:
Park, Dongkook
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
February 08, 2008
Committee Members:
  • Chitaranjan Das, Committee Chair
  • Vijaykrishnan Narayanan, Committee Member
  • George Kesidis, Committee Member
  • David Jonathan Miller, Committee Member
Keywords:
  • Network-on-Chip
  • on-chip interconnection
  • low-power
  • reliability
  • router architecture
Abstract:
The notion of a Network-on-Chip (NoC) is rapidly gaining a foothold as the communication fabric in complex System-on-Chip (SoC) architectures including recent Multi-Core architectures. Scalability is the NoC's most valuable asset, which makes it ideal for larger designs. However, the NoC architectures have intrinsic challenges from various aspects such as reliability issues stemming from the deep sub-micron technology, and more stringent requirement for high-performance and low-power consumption for multi-core chips. A plethora of research has been conducted in these areas and along this line, in this thesis, I present a set of techniques targeting high-performance, energy-efficient, and reliable NoC architectures. The advent of deep sub-micron technology has exacerbated reliability issues in on-chip interconnects. In particular, single event upsets, such as soft errors, and hard faults are rapidly becoming a force to be reckoned with. This spiraling trend highlights the importance of detailed analysis of these reliability hazards and incorporation of comprehensive protection measures into all Network-on-Chip (NoC) designs. In this thesis, I examine the impact of transient/permanent failures on the reliability of on-chip interconnects and develop comprehensive counter-measures to either prevent or recover from them. In this regard, I propose several novel schemes to remedy various kinds of error symptoms, while keeping area and power overhead at a minimum. The proposed solutions are architected to fully exploit the available infrastructures in an NoC and enable versatile reuse of valuable resources. On the other hand, increasingly diminishing feature sizes have rendered the interconnect as the primary bottleneck in terms of both latency and power consumption in on-chip systems. It is, therefore, imperative to optimize the network infrastructure to maximize performance. Research has primarily focused on architectural improvements within the router and the development of deadlock avoidance/recovery schemes. The latter tend to rely on fairly complex algorithms, which are sometimes infeasible to implement in NoCs due to their resource-constrained nature. In this thesis, I introduce a new NoC topology and architecture which injects data into the network using four sub-NICs (Network Interface Controllers), rather than one NIC, per node. The proposed scheme achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. Most importantly, this implementation is inherently deadlock-free, thus eliminating the need to rely on specialized, resource-hungry algorithms for deadlock avoidance. In an effort to improve network performance, I also propose a dynamic path management scheme that exploits network traffic information during switch arbitration. Consequently, flits transferred across frequently used paths are expedited by traversing a reduced router pipeline. This technique also allows pipeline bypassing for frequent paths, further improving the performance while incurring only minimal area / power overhead. Recent introduction of 3D chip design methodologies encourages 3D NoC architecture. Since three dimensional (3D) integration has emerged to mitigate the interconnect delay problem, exploring the NoC design space in 3D can provide ample opportunities for designing high performance and energy-efficient NoC architectures. However, without proper countermeasures against its inherent flaws such as thermal problem and increased vulnerability to error sources, its advantage would be despoiled. In this thesis, I propose a 3D stacked NoC router architecture, called MIRA, which unlike the 3D routers in previous works, is stacked into multiple layers and optimized to reduce overall area requirements and power consumption. I discuss the design details of a four-layer 3D NoC and its enhanced version with additional express channels, and compare them against a (6×6) 2D design and a base line 3D design. The proposed multi-layered NoC routers can outperform the 2D and naïve 3D designs in terms of performance and power. In summary, the overall aim of this research is to design high-performance, energy-efficient, and reliable on-chip networks considering advanced technologies applicable to NoCs.