Towards Minimizing the Adverse Effects of
Temperature on High Performance Digital Systems
Open Access
Author:
Ricketts, Andrew Jonathan Sylvester
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
October 22, 2009
Committee Members:
Vijaykrishnan Narayanan, Dissertation Advisor/Co-Advisor Vijaykrishnan Narayanan, Committee Chair/Co-Chair Mary Jane Irwin, Committee Member Yuan Xie, Committee Member Kenan Unlu, Committee Member
Keywords:
High temperature relaibility NBTI temperature induced clock skew
Abstract:
There are wide power variations across a chip leading to temperature variations. High
power density components such as register files and arithmetic logic units will trend
towards elevated temperatures while other lower power density units will be cooler.
Higher temperatures in general decrease the lifetime reliability of digital systems through
a number of mechanisms. Furthermore, continued scaling leads to an increase in soft
error occurrences. To this end in addition to increasing the error resiliency of register
files a proposal that would also lower energy per access is presented. The power modes
available to save power also have the effect of lowering the rate of certain degradation.
The effect of negative bias temperature instability (NBTI) on SRAM cells under power
saving modes is investigated for leakage current, read and hold margins. This is done for
both symmetric and asymmetric cells. Noting that temperature variations occurs across a
chip, we present techniques to lower its effects on synchronous digital circuits
propagation delay variation in general and clock skew in particular.
