Variation Study on Advanced Cmos Systems for Low Voltage Applications

Open Access
Author:
Agrawal, Nidhi
Graduate Program:
Electrical Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
July 13, 2015
Committee Members:
  • Suman Datta, Dissertation Advisor
  • Thomas Nelson Jackson, Committee Chair
  • Vijaykrishnan Narayanan, Committee Member
  • Roman Engel Herbert, Special Member
Keywords:
  • FinFET
  • TFET
  • Line Edge Roughness (LER)
  • Line Width Roughness (LWR)
  • SRAM
  • Rean Static Noise Margin (RSNM)
  • NBTI
  • PBTI
Abstract:
One of the key challenges in scaling beyond 10nm technology node is device-to-device variation. Variation in device performance, mainly threshold voltage (VT) inhibits supply voltage (VCC) scaling. In this work, a comprehensive study of process variations and line edge roughness (LER)/sidewall roughness (SWR) effects in advanced CMOS devices namely Silicon (Si) Bulk n-/p-FinFETs, In0.53Ga0.47As Bulk n-FinFETs, Germanium (Ge) Bulk p-FinFETs and Gallium Antimonide-Indium Arsenide (GaSb-InAs) staggered-gap Heterojunction n-/p-Tunnel FETs (HTFETs) is presented. This study is done using three-dimensional (3D) Technology Computer Aided Design (TCAD) numerical simulations. According to the sensitivity study, FinFET and Tunnel FET (TFET) device parameters are highly susceptible to n width, WFIN, and ultra-thin body thickness, Tb, variations, respectively. Moreover, TFETs show higher variation in device than FinFETs. Additionally, a Monte Carlo study of SWR variation on n- and p-FinFETs show higher 3sigma(VTLin) of In0.53Ga0.47As Bulk n- and Ge Bulk p-FinFETs than their Si counterparts. Further, to study the variation impact on memory circuits, we also simulate 6T and 10T SRAM cells with FinFETs and HTFETs, respectively. Another key challenge with advanced CMOS devices is time-dependent VT degradation due to BTI reliability. Thus, in the second part of this work, a comparative study of Positive Bias Temperature Instability (PBTI) reliability on n-type III-V devices and Negative Bias Temperature Instability (NBTI) reliability on p-type Ge devices is presented. PBTI reliability is studied in InxGa1