Open Access
Theocharides, Theocharis
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
December 09, 2005
Committee Members:
  • Vijaykrishnan Narayanan, Committee Chair
  • Mary Jane Irwin, Committee Chair
  • Yuan Xie, Committee Member
  • William Kenneth Jenkins, Committee Member
  • Wayne Wolf, Committee Member
  • face detection
  • embedded systems
  • hardware implementations
The digital surveillance market is expected to reach USD $7 billion by 2008, at an average annual growth rate of 55%. More importantly however, this growth is enhanced by the increasing needs of security and control systems used in heavily trafficked areas such as airports, transportation hubs and public buildings. Human face detection in real-time video is one of the most important applications in the field. Performed mostly in software so far, it has not been applied in real-time video frame rates. With today’s technology however, we are capable of designing hardware platforms to perform face detection in real-time video and allow for deployment of multiple cameras to be used for detection. Multi-camera face detection offers significant cost cutting solutions for deploying a surveillance mechanism consisting of multiple cameras and a single high-speed platform. Such a platform, however, must provide reliable data transmission from each camera to the base station; as such, an error correction mechanism which achieves excellent block performance (capable of detecting and correcting large chunks of data) and operates at high-throughput is necessary. This thesis presents a framework for an embedded face detection platform for digital surveillance systems, including reliable video transmission. Firstly, the design of a Low-Density Parity Check (LDPC) Decoder is presented. The decoder architecture is suitable for providing a reliable and high-bandwidth communications channel between multiple cameras and the base station. Next, this thesis focuses on explorations for hardware architectures for face detection algorithms. One of the most popular face detection algorithms is the AdaBoost classification technique, offering significant advantages in terms of speed and accuracy over other algorithms. Given the advantages of AdaBoost, this thesis presents the design of an architecture which performs face detection using AdaBoost, achieving high frame rates in conditions where the corresponding software approach slows significantly. The AdaBoost technique however demands a large number of hardware resources, hence an alternative method, Artificial Neural Network (ANN) based face detection is investigated. The proposed architecture designed to implement ANN based face detection, processes 24 frames per second and is presented along with an FPGA prototype implementation. ANNs are also used in several other applications other than face detection, such as face recognition which usually follows face detection. As such, the design of an ANN architecture using Networks-On-Chip is presented next. The presented architecture can be used to perform face detection using ANNs, as well as several other ANN applications. All presented architectures achieve high frame rates, and maintain detection accuracy comparable to software implementations.