DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS

Open Access
Author:
Li, Lin
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
June 24, 2005
Committee Members:
  • Mary Jane Irwin, Committee Chair
  • Vijaykrishnan Narayanan, Committee Chair
  • Mahmut Taylan Kandemir, Committee Member
  • Yuan Xie, Committee Member
  • Kenan Unlu, Committee Member
Keywords:
  • Energy-Efficiency
  • Reliability
  • Cache
  • Interconnect
Abstract:
The minimum feature size of VLSI technology has shrunk exponentially in the past three decades and this trend is expected to continue in the near future. This phenomenon has resulted in an increase in the number of transistors integrated onto a single chip, a decrease in supply voltages and threshold voltages, and an increase in clock frequencies for each generation. The scaling of these design parameters impacts digital circuits and systems design in two important ways: a dramatic increase in energy consumption and a deterioration of reliability. This thesis proposes design methodologies and techniques at the micro-architecture level for improving energy-efficiency and reliability in cache memories and on-chip interconnects. First, architectural techniques are proposed to reduce both leakage and dynamic energy consumption in cache memories. State-preserving and state-destroying leakage control mechanisms are integrated into L2 cache to reduce leakage energy consumption due to the data duplication across different levels of cache hierarchy. A crossbar-connected cache configuration is proposed for on-chip multiprocessor systems. The dynamic energy consumption in L1 cache is reduced due to sharing a single, banked cache among processors. Next, the impact of crosstalk noise on the reliability of on-chip interconnects is investigated, and a crosstalk-aware interconnect is proposed. A crosstalk analyzer circuit is designed to be incorporated into the sender side of the bus to estimate the delay based on the data pattern to be transmitted. Then, a variable cycle transmission mechanism is implemented to use a faster clock and dynamically control the number of cycles required for transmission. Finally, the interaction between energy consumption and reliability is studied. Based on the soft error injection implemented in the cache system of SimpleScalar simulator, the impact of two architectural-level leakage reduction approaches, drowsy cache and cache decay, on the data reliability are evaluated. Then, providing data reliability in an energy-efficient fashion is investigated. An adaptive error coding scheme is proposed that treats dirty and clean data cache blocks differently. Furthermore, an early-write-back scheme is introduced to enhance the ability to use a less powerful error protection scheme for a longer time without sacrificing reliability. Adaptive error protection scheme is also applied to on-chip interconnects for energy efficiency, where the type of error detection coding scheme is modulated dynamically based on the dynamic variations observed in noise behavior.