Soft Errors: Modeling And Interactions with Power Optimizations
Open Access
- Author:
- Degalahal, Vijay Sai
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- August 12, 2005
- Committee Members:
- Vijaykrishnan Narayanan, Committee Chair/Co-Chair
Mary Jane Irwin, Committee Member
Kenan Unlu, Committee Member
Yuan Xie, Committee Member - Keywords:
- reliability in DSM
Soft errors
Single event upsets
low power VLSI - Abstract:
- Soft errors are radiation induced ionization events that cause errors in circuits. The circuit always recovers from these errors as they do not damage the circuit. However, computation from the erroneous state of the circuit may corrupt the data, which is harder to correct or recover. In nanometer technologies, the reduced nodal capacitances and supply voltages coupled with more dense and larger chips are increasing soft errors and making them an important design constraint. This thesis models the phenomena of soft errors at device level. This model is used to create a transient current library which will useful for circuit level soft error estimation. The library contains the transient current response to various different factors such as ion energies, operating voltage, substrate bias, angle and location of impact. Excessive power consumption by CMOS devices is a major design limiter for current and, next generation devices. As designers aggressively address the power problem, they need to be aware of the impact of power optimizations on the soft error rates(SER). Hence, this thesis examines the influence of some popular power optimization schemes on SER. Lastly, this thesis explores the effect on SER due to supply voltage scaling, one of the popular power optimization scheme, with accelerated neutron testing on a commercial memory chip. In summary, the thesis contributes in three significant directions towards understanding soft errors and its interactions with power optimizations.