Open Access
Iyengar, Anirudh Srikant
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
June 04, 2018
Committee Members:
  • Swaroop Ghosh, Dissertation Advisor
  • Vijaykrishnan Narayanan, Committee Chair
  • Trent Ray Jaeger, Committee Member
  • Swaroop Ghosh, Committee Member
  • Saptarshi Das, Outside Member
  • Spintronics
  • Security
  • Camouflaging
  • PUF
  • NVFF
  • Secrecy and Privacy
  • Modeling
With increased integration of technology in our lives, the arms race between chip manufacturers to provide the latest and greatest to entice the consumer, only intensifies. A by-product of this growth is an ever-increasing demand for performance and efficiency. To address this problem CMOS transistors have always been scaled to smaller nodes to ‘fit in’ more functionality as well as lower the overall energy-footprint of the operation. However, scaling down the size of the transistor is becoming difficult, which in-turn dramatically reduces the profit motive of such an endeavor. Additionally, several new challenges are emerging in integrated circuit (IC) design: mainly leakage power (in caches) and the need for high-bandwidth computing. With this foresight, the industry began investigating alternative memory technologies such as: Resistive RAM (RRAM), Phase Change RAM (PCRAM), Spin Transfer Torque RAM (STTRAM), Domain Wall Memory (DWM), Magnetic RAM (MRAM), Ferroelectric RAM (FeRAM), Memristor etc., that could replace CMOS in cache applications whilst providing non-volatility (to eradicate leakage), high-density (high-bandwidth compute) and high-endurance (long lifetime). A side-effect of incorporating these new memory technologies is the issue of security, privacy and counterfeiting. As the demand for technology increases, the motivation for adversaries to tamper with them for economic, political and social gains will only increase. A major perspective for the “beyond CMOS” comes from spintronic memory (as per the International Technology Roadmap for Semiconductors) exploiting not only the charge of electrons but more importantly their magnetism, or their spin. STTRAM and DWM offer much potential owing to their high endurance, retention and density while operating at low-voltages. This motivated me to explore various possibilities of spintronic memory (STTRAM and DWM) in the domain of energy-efficiency, security and testing. This thesis addresses: (i) energy-efficient applications and techniques for a system employing spintronic memory; (ii) the security challenges we might face adopting spintronic memory; and (iii) the need for securing traditional CMOS ICs from a counterfeiting as well as a duplication standpoint. In particular, we tackle the problems in energy-efficiency, authentication, privacy and secrecy. The first part of the thesis describes the modeling aspects of spintronic memory i.e. STTRAM and DWM. Then, we present three energy-efficient spintronic memory applications: (i) non-volatile flip-flop (NVFF), (ii) MTJ crossbar using selector diode (SD) and, (iii) pulsed shifting of DWs. Apart from the traditional state retentivity, the proposed NVFF offers protection against unexpected power-cuts— allowing for a fluid instant-ON experience. The MTJ crossbar using a MIIM SD allows for a high-density design with the necessary robustness and energy-efficiency demanded by high bandwidth applications. The pulsed shifting technique of DWs reduces the impact of Joule heating in NWs, thus, maintaining energy efficiency without sacrificing performance. In the next part of the thesis we present potential security vulnerabilities– side channel analysis and data privacy, of STTRAM and DWM. We present some mitigation techniques to circumvent these issues. Following this, we explore the security aspects of said spintronic memory, by illustrating their potential use as a PUF. Our proposed PUFs exploit the inherently large entropy surrounding the DW NW making them a strong candidate for magnetic memory-based authentication. We then analyze the operation and robustness of the PUFs under varying supply and temperature conditions. Finally, we describe threshold voltage defined CMOS switches for camouflaging logic. By modifying the doping concentration of selective CMOS switches at design-time, we have been able to realize six different logic functionalities. We demonstrate the designs by implementing ring oscillators (RO) in a 65nm node test-chip on which we analyze the impact of supply-voltage, process variation and temperature. Also, we demonstrate how we can reclaim lost performance by tuning the gate voltage under varying temperatures and supply voltages. The difficulty in RE the netlist when a portion of the gates are camouflaged gate is quantified by estimating the time taken for the decamouflaging process. We also describe camouflaged gate selection using controllability and observability conditions. Additionally, an alternative camouflaging technique that operates on charge-trap is described. The advantage of this technique is that the charge trapped in the gate oxide is responsible for gate selection, thus leaving no physical evidence of camouflaging. In summary, this dissertation provides an overview of the design, analysis and applications of STTRAM and DWM for energy-efficiency and enhanced device security.