Open Access
Ramanarayanan, Rajaraman
Graduate Program:
Electrical Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
November 28, 2006
Committee Members:
  • Vijaykrishnan Narayanan, Committee Chair
  • William Kenneth Jenkins, Committee Chair
  • Mary Jane Irwin, Committee Member
  • Charles Lee Croskey, Committee Member
  • Yuan X Ie, Committee Member
  • Kenan Unlu, Committee Member
  • modeling
  • reliability
  • logic circuits
  • soft errors
  • analysis
Soft errors in data paths are gaining importance as technology scales down, because of increased speed, the number of stages in pipelines, and the decrease in device sizes and supply voltages. In this work, first we consider flip-flop and adder circuits, representing the data-path elements in present day processors for detailed circuit level soft error analyses. We perform simulations to analyze the effect of increasing threshold voltage in flip-flops and dynamic voltage and frequency scaling on the soft error rate in the adder circuits. Second, we also experiment with techniques to improve the soft error rate in these circuits. Next, we propose a new approach to model soft errors in larger circuits, which can be applied to designs that use cell libraries. These cell libraries are characterized for soft error analysis and utilize analytical equations to model the propagation of a voltage pulse to the input of a state element. The average error of the SER estimates, using our approach compared to the estimates obtained using circuit level simulations, is 6.5% while providing an average speed up of 15000. We have demonstrated the scalability of our approach using designs from the ISCAS-85 benchmarks. Increasing variability in device parameters not only affects the behavior of contemporary ICs, but also their vulnerability to transient error phenomenon, especially soft errors. Such variations in device parameters are caused by static process variations, dynamic variations in power supply and temperature values and slow degradation of individual devices due to phenomena like Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). In the next part of our work, we analyze the impact of iv such variations on the Soft Error Rates (SER) of combinational logic circuits. Tools that model threshold degradation of NMOS devices due to HCI and PMOS devices due to NBTI in logic circuits were built based on existing methodologies. Results were obtained for custom designed circuits and ISCAS-85 benchmarks. A detailed analysis of the effects of threshold variations on SER is also presented with interesting observations. Finally, the results of experimental measurements of SER in different set-ups and different devices including a microcontroller and a microprocessor are presented in the Appendix. While the experiments on the microcontroller showed no errors, the microprocessor had many failures, thus clearly indicating the trend in soft errors with technology scaling. The results presented here show the increase in error rates with voltage scaling as well.