Arsendie-Antmonide Tunnel Transistors for Low Power Logic Applications

Open Access
Mohata, Dheeraj Kumar
Graduate Program:
Electrical Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
January 17, 2013
Committee Members:
  • Suman Datta, Dissertation Advisor
  • Vijaykrishnan Narayanan, Committee Member
  • Theresa Stellwag Mayer, Committee Member
  • Jun Zhu, Committee Member
  • Transistor
  • TFET
  • Arsenide
  • Antimonide
  • Hetero-junction
  • Fabrication
  • low power
  • steep switching
  • supply voltage
Aggressive supply voltage (VCC) scaling of future transistors without increasing the off-state leakage while maintaining performance remains an important challenge. Hetero-junction Tunnel FETs (HTFETs) with steep switching slope and high drive current at low supply voltage (below 0.35V) have emerged as promising low VCC device option. GaAs1-ySby source and InxGa1-xAs channel form lattice matched arsenide-antimonide staggered hetero-junctions with compositionally tunable effective tunnel barrier height. Unlike homo-junction Tunnel FETs, the effective barrier height of staggered hetero-junctions can be made negligibly small while maintaining large band-gaps in the respective source, channel and drain regions, thus, enabling TFETs to achieve MOSFET like drive currents while maintaining higher on-off ratio. This dissertation focuses on experimental demonstration of mixed arsenide-antimonide hetero-junction TFETs with nano-pillar tunnel transistor architecture exhibiting MOSFET-like on-current and high on-off ratio for ultra-low power logic applications. Within this dissertation, using experimental demonstration and detailed modeling, following aspects of the n-channel hetero-junction Tunnel FETs will be discussed: a) Material selection and device design; b) Nano-pillar TFET process flow development; c) Hetero-junction TFET growth and materials characterization; and d) Hetero-junction TFET transport study. The dissertation concludes with benchmarking of the performance of arsenide-antimonide n-channel Tunnel FETs with those reported till date, and an address to the feasibility of arsenide-antimonide based complementary Tunnel FET logic for future ultra low power logic applications.