Open Access
Zhang, Wei
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
June 18, 2003
Committee Members:
  • Mahmut Taylan Kandemir, Committee Chair
  • Mary Jane Irwin, Committee Member
  • Anand Sivasubramaniam, Committee Member
  • Vijaykrishnan Narayanan, Committee Member
  • Richard R Brooks, Committee Member
  • Reliability
  • Dcache
  • Compiler
  • Low Power
  • Icache
Power and energy consumption has become a significant constraint in modern microprocessor design. While energy conscious design is obviously crucial for battery driven mobile and embedded systems, it has also become important for desktops and servers due to packaging and cooling requirements where power consumption has grown from a few watts per chip to over 100 watts. Recent trends indicate that the architecture and software techniques, in addition to low-level circuit techniques, can play a major role in power-efficient computer system design. VLIW architectures are increasingly used in systems where energy-efficiency is an important consideration. In a VLIW architecture, compiler plays an important role in achieving acceptable instruction level parallelism. The energy efficiency of VLIW processors is determined by the underlying hardware and compiler techniques. While many performance optimizations in VLIW architecture also bring energy benefits as a side effect, it is possible to achieve further benefits by explicitly focusing on energy. This thesis proposes three such compiler-directed energy optimizations for VLIW architectures. The first optimization is based on the observation that ``slacks`` present in the CPU datapath in VLIW machines due to the lack of available independent instructions, data dependence and schedule-specific decisions. Therefore, an optimizing compiler can analyze the program to identify the slack for each instruction. To exploit slacks, we can scale down voltage/frequency or turn off functional units. Therefore, energy consumption can be reduced by exploiting these slacks with no impact on performance or under a performance constraint. To find larger slacks to benefit leakage energy control, our second optimization is built upon a data-flow analysis to identify the idleness of a particular functional unit across basic blocks. Collecting this information from all basic blocks in the code, it then inserts explicit activate/deactivate instructions in the code to set/reset a sleep signal which controls leakage current for functional units. Our third energy optimization targets at reducing leakage energy consumption in instruction caches. We propose and analyze two compiler-based strategies termed as ``conservative`` approach and ``optimistic`` approach. The conservative approach does not put an instruction cache line into a low leakage mode until it is certain that the current instruction in it is dead (i.e., it will not be accessed in the rest of the execution). In comparison, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap. We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms. Our results indicate that compiler-based cache leakage management can be very successful in practice. While leakage energy can be reduced significantly by applying leakage control mechanisms, the aggressive use of such techniques can make the hardware circuits more susceptible to soft errors. Consequently, in the final portion of this thesis, we propose a novel solution to enhance the reliability for caches without compromising on performance. The idea is to replicate hot cache lines in rarely-used ones to provide a better error resilience.