Energy-aware hardware and software optimizations for embedded systems

Open Access
Author:
Kim, Hyun Suk
Graduate Program:
Computer Science and Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
May 05, 2003
Committee Members:
  • Vijaykrishnan Narayanan, Committee Chair
  • Mary Jane Irwin, Committee Chair
  • Mahmut Taylan Kandemir, Committee Member
  • Richard Brooks, Committee Member
Keywords:
  • compiler optimizations
  • embedded systems
  • dynamic power
  • leakage power
  • power optimiations
  • VLIW architectures
  • Presburger arithmetic
  • Polyhedran modeling
  • loop tiling
  • instruction level parallelism
  • Trimaran
Abstract:
Widespread use of portable embedded systems and rapidly shrinking feature sizes have brought about a large body of research on low power systems design. Embedded systems realize the convergence of computers, communications, and multimedia into portable products, therefore, system designers should have better knowledge of power consumption of the entire system. This thesis proposes and studies a set of energy evaluation and optimization techniques in architectural and software level for two main components of embedded systems: memory elements and processing elements. First, the thesis deals with evaluation and optimization of memory systems. Applications are increasingly becoming data-intensive as image processing capabilities are incorporated into portable systems. Since memory accesses consume a significant amount of power, we propose memory energy models for a representative set of on-chip cache architectures and evaluate their energy behavior. As a large volume of data needs to be stored off-chip, we also propose an off-chip memory energy estimation models to enable the designers to evaluate off-chip energy behavior of individual applications. Second, the study focuses on the energy evaluation and optimization of processing elements. Variants of VLIW architectures are increasingly becoming popular for DSP processors due to their support for wide instruction level parallelism and reduced hardware complexity. An energy simulator for VLIW architectures is developed, which is built on top of a publicly available compilation toolset. Since the compilation toolset has a set of state-of-the-art compilation techniques, we evaluate their energy consumption using the energy simulator, varying architectural parameters. Next, we propose and evaluate a new leakage optimization technique using this toolset. This optimization technique is important as leakage energy is expected to increase exponentially in the next decade. The tools and techniques proposed in this thesis are expected to be useful for designing energy-efficient embedded systems.