Implications of Future Technologies on the Design of FPGAs

Open Access
Gayasen, Aman
Graduate Program:
Computer Science and Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
August 08, 2006
Committee Members:
  • Mahmut Taylan Kandemir, Committee Chair
  • Vijaykrishnan Narayanan, Committee Chair
  • Mary Jane Irwin, Committee Member
  • Vittaldas V Prabhu, Committee Member
  • field programmable gate array
  • power
  • thermal
  • three-dimensional stacking
  • three-dimensional integration
  • nanotechnology
  • interconnect
The Field Programmable Gate Array (FPGA) industry is going through an exciting phase. The market leaders, Xilinx and Altera, announce new products almost every year. Their CAD tools also keep adding new features. The growing popularity of FPGAs demands that we sustain the growth of FPGAs. This thesis explores new technologies for continuing the improvement of FPGAs in future. In this thesis, we study the effect of three main future technologies. First, we evaluate FPGA designs for scaled CMOS technologies — 65nm and below. The main problems here are leakage, temperature, and process variation. Second, we look at 3-D stacking of multiple dies within a package. Since this technology is still being perfected, we have several parameters to play with. For example, the properties of the vias that provide communication among the different layers (inter-layer vias) are very different from the other wires, especially pitch and length. This brings about an asymmetry in the FPGA fabric. How this influences the FPGA architecture is a question we try to answer. Furthermore, stacking multiple layers increases the power density, which increases the junction temperature. This thesis studies the impact of stacking on temperature, and proposes thermal-aware organization of FPGAs. Finally, we look at some technologies that are still in their infancy, such as molecular switches, carbon nanotubes, and silicon nanowires. Specifically, we explore the use of such technologies to implement the interconnect fabric in an FPGA.