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Start Over You searched for: Graduate Program Computer Science and Engineering Remove constraint Graduate Program: Computer Science and Engineering Committee Member Vijaykrishnan Narayanan Remove constraint Committee Member: Vijaykrishnan Narayanan

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1. Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems

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2. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors

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3. Exploring Power Reliability Tradeoffs in On-Chip Networks

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4. Redundancy and Parallelism Tradeoffs for Reliable, High-Performance Architectures

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5. Implications of Future Technologies on the Design of FPGAs

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6. RELIABILITY ANALYSIS AND OPTIMIZATION FOR NANOSCALE SYSTEM-ON-CHIP DESIGN

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7. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures

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8. Sensor Network Interoperability and Reconfiguration through Mobile Agents

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9. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS

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12. EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES

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13. Energy-aware hardware and software optimizations for embedded systems

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14. System Level Power and Reliability Modeling

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15. ANALYSIS OF TWO-DIMENSIONAL MEDIAN FILTER HARDWARE IMPLEMENTATIONS FOR REAL-TIME VIDEO DENOISING

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16. A Comprehensive Approach to Design Network-on-Chip Architectures for SoC/Multicore Systems

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17. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications

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18. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY

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20. A Configurable Platform for Sensor and Image Processing

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21. Quality of Service Provisioning in Clusters

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22. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS

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23. Secure Communications in Sensor Networks

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24. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS

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25. Addressing Reliability Issues in Performance-Critical Processor Structures

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26. Accessing Spatial Information in Resource-constrained and Resource-rich Environments

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27. A Reliable Design Flow for Platform FPGAs.

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28. Application-Aware On-Chip Networks

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30. Influence of Emerging Technologies on Interconnect Architectures

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34. Power Management of Enterprise Storage Systems

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35. CLOSING THE GAP BETWEEN FPGAs AND ASICs: THE APPLICATIONS OF CLOCK SKEW SCHEDULING ON FPGAs

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36. EMBEDDED HARDWARE FACE DETECTION FOR DIGITAL SURVEILLANCE SYSTEMS

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38. DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES

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40. ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION

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42. Design Exploration for Three-dimensional Integrated Circuits (3DICs)

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43. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs

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44. VARIATION-AWARE BEHAVIORAL SYNTHESIS FOR NANOMETER VLSI CHIPS

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45. Mobile Agent-Based Energy-Efficient and Secure Global Information Systems

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47. Architecting On-Chip Interconnection Network for Future Many-Core Chip-Multiprocessors

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48. Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems

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49. A Game Theoretic Approach to Multi-agent Systems in Highly Dynamic, Information-sparse, Role Assignment Scenarios

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50. Accelerating Design and Implementation of Embedded Vision Systems

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51. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity

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52. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System

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53. system-on-chip integration of heterogeneous accelerators for perceptual computing

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54. Utilizing Graphics Processing Units for Rapid Facial Recognition using Video Input

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55. A Study of DRAM Optimization to Break the Memory Wall

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56. Rethinking the memory hierarchy design with nonvolatile memory technologies

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57. Configurable Accelerators for Visual and Text Analytics

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58. using attention to enhance efficiency in video-based computer systems

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59. An examination of Post-CMOS computing techniques using steep-slope device-based architectures

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60. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory

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62. design methodologies of three-dimensional integrated circuits (3D ICs)

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64. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline

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66. Real Time Object Tracking On Active Pan Tilt Zoom Camera Using Cmt

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67. A High-efficiency Switched-capacitance Htfet Charge Pump For Low-input-voltage Applications

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68. Optimization and Hardware Acceleration of Consensus-based Matching and Tracking

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69. Architecting Byte-addressable Non-volatile Memories for Main Memory

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70. Three Dimensional Integrated Circuit Design and Test

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72. Large-Scale Object Recognition for Embedded Wearable Platforms

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73. EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS

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74. DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS

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75. PREDICTION AND ASSESSMENT OF AMBIENT ENERGY SIGNALS FOR ENERGY HARVESTING SYSTEMS

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76. DATA DEPENDENT OPTIMIZATION VISION ARCHITECTURE

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77. Design and Exploration of Accelerator-rich Multi-core Systems

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78. Object Recognition Using Structured Feature Extraction With A Reconfigurable, Neurosynaptic Processor

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81. Enabling New Computation Paradigms with Emerging Technologies

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83. Self-powered Internet-of-Things Nonvolatile Processor and System Exploration and Optimization

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86. ENERGY-EFFICIENT AND SECURE DESIGNS OF SPINTRONIC MEMORY: TECHNIQUES AND APPLICATIONS

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87. Maritime Navigation and Contact Avoidance through Reinforcement Learning

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89. CONTEXT-AWARE COLLABORATIVE OBJECT RECOGNITION FOR MULTI CAMERA TIME SERIES DATA

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92. Context-Aware Design and Optimization of Embedded Deep Neural Network Architectures

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94. PowerPrep : A power management technique for user-facing datacenter workloads

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95. Processing In-Memory Architecture Incorporating Systolic Dataflow for Deep Neural Networks

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96. Optimization of Inter-Cache Traffic Entanglement in Tagless Caches with Tiling Opportunities

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98. Technology Driven Architecture Support for Memory Hierarchies

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