Modeling And Design Analysis Of Emerging Non-volatile Memories For Future Computer Systems

Open Access
Author:
Zheng, Yang
Graduate Program:
Computer Science and Engineering
Degree:
Master of Science
Document Type:
Master Thesis
Date of Defense:
March 02, 2015
Committee Members:
  • Yuan Xie, Thesis Advisor
  • Vijaykrishnan Narayanan, Thesis Advisor
Keywords:
  • STT-RAM
  • ReRAM
  • Non-volatile Memory
Abstract:
As traditional SRAM and DRAM are facing leakage power and fabrication difficulties beyond 22nm technology, emerging memory technologies such as spin transfer-torque RAM (STT-RAM), phase-change RAM (PCRAM), and resistive RAM (ReRAM) have been widely studied as promising candidates for the next generation memory technologies. Among all these NVM technologies, STT-RAM is expected to be used as on-chip caches for its fast access latency and better scalability. While ReRAM is predicted to replace NAND flash in the foreseeable future due to its extremely high density. However, several challenges have to be dealt with before these emerging memory technologies being commercialized. Although the read latency of STT-RAM is relatively fast, the write latency remains to be slow. Also, traditional 1-Transistor-1-MTJ cell structure suffers from severe leakage current and dynamic power as the technology node continuously shrinks down. On the other hand, ReRAM also suffers from reliability problems. Due to the stochastic nature of memristor, ReRAM device not only suffers from spatial variation, but also temporal variation. As the cross-point structure is commonly used for ReRAM devices since it offers higher density and lower cost, the reliability issue of ReRAM becomes a constraint on preventing ReRAM being commercialized as large-scale memory. The thesis proposes models and analysis on three novel array-level structures to mitigate the problems existed in STT-RAM based memory technology from different aspects. The parallel shared 1TNJ structure decreases the cell area by rerouting the wires between the access transistor and the MTJ so that one transistor is responsible for multiple MTJs. On the other hand, the 1S1J cross-point structure uses selector as the access transistor for better scalability. Moreover, The FinFET device is introduced to cut off leakage current and reduce the cell area. The thesis also proposes a model for analyzing the reliability and variability issues in ReRAM based memory technology. The thesis provides a detailed analysis on different reliability issues, and proposes several mitigation solutions.