IMPROVED TIQ FLASH ADC TRANSISTOR SIZING ALGORITHMS TO REDUCE LINEARITY ERRORS

Open Access
Author:
Park, Jun Hyuk
Graduate Program:
Computer Science and Engineering
Degree:
Master of Science
Document Type:
Master Thesis
Date of Defense:
April 21, 2017
Committee Members:
  • Kyusun Choi, Thesis Advisor
  • Vijaykrishnan Narayanan, Committee Member
Keywords:
  • TIQ Flash ADC
  • TIQ Voltage Comparator
  • Nonlinearity
  • DNL
  • INL
  • Process Variation
Abstract:
Integral nonlinearity and differential nonlinearity are the two main performance parameters for a high speed flash analog-to-digital converter, which determine the accuracy of the converter. Analog-to-Digital Converter (ADC) circuits are designed to achieve ideal performance - zero linearity. However, the linearity is unavoidable due to the process variation, operating temperature variation, and power supply voltage variation when the data converters are manufactured and used in non-ideal environments. We present the new and improved transistor sizing algorithms for the Threshold Inverter Quantization (TIQ) flash comparator circuit design software package, the sizing algorithm that will results in minimal linearity for the TIQ ADCs after they are manufactured and used in non-ideal environments. In comparison to the previous algorithms, the proposed new transistor sizing algorithms reduce the worst-case linearity by 80% or more. In the future, when implementing ADC circuits with below-30nm CMOS FinFET technology, the TIQ flash ADC is the first candidate because only two transistors are present between the power supply rails, and the transistor sizing is based on the discrete count of fins.