Performance-reliability trade-offs in designing Re-Order Buffers

Open Access
Sridharan, Srinath
Graduate Program:
Computer Science and Engineering
Master of Science
Document Type:
Master Thesis
Date of Defense:
February 29, 2008
Committee Members:
  • Vijaykrishnan Narayanan, Thesis Advisor
  • Chitaranjan Das, Thesis Advisor
  • ROB
  • Late Binding
  • vulberability
Recent research efforts to enable quantitative analysis of the architectural transient fault-tolerance solutions has led to a key metric named Architectural Vulnerability Factor (AVF). AVF quantifies the relative contributions of the key processor structures to the overall processor error rate. In this paper, we propose a new design of Re-Order Buffer (ROB), a key structure in superscalar architectures, to reduce its AVF without disrupting the AVF of other structures. This new design, which is employed using a technique named Late Instruction Binding (LIB), provides better reliability without compromising on performance. LIB postpones the binding of instruction information to the ROB from the time of allocation to the time when the results are written back from the execution units. In order to enable LIB, we propose a Target Address Buffer (TAB) which stores only the target addresses of the taken branch instructions. With TAB and the Program Counter (PC) of the last committed instruction, the PC of the exception raising instruction can be easily obtained, thus eliminating the need to buffer the PCs all in-flight instructions in ROB. This also reduces the overall ROB size. Detailed simulation with SPEC CPU 2000 benchmarks show that LIB achieves an average of 33.4% and up to 56.5% reduction in AVF over the conventional instruction binding in ROB. Furthermore, with a slight increase in the width of the issue queue and execution units, LIB achieves an average of 38.7% and up to 64.5% reduction in AVF of ROB. This increase in width also lend towards an average improvement of 9.5% and up to 57.2% in IPC.