A High-efficiency Switched-capacitance Htfet Charge Pump For Low-input-voltage Applications

Open Access
Heo, Unsuk
Graduate Program:
Computer Science and Engineering
Master of Science
Document Type:
Master Thesis
Date of Defense:
March 30, 2015
Committee Members:
  • Vijaykrishnan Narayanan, Thesis Advisor/Co-Advisor
  • Kyusun Choi, Thesis Advisor/Co-Advisor
  • Charge pump
  • DC-DC converter
  • power-conversion-efficiency (PCE)
  • switched-capacitance
  • tunnel FET (TFET)
High-efficiency power delivery, as well as low-power circuit design continues to be an important concern in energy harvesting circuits and application that are limited by the battery capacity. This thesis presents a high-efficiency switched-capacitance charge pump in 20 nm III-V heterojunction tunnel field-effect transistor (HTFET) technology for low-input-voltage applications. It provides for higher efficiency than the conventional CMOS solution. The proposed circuit doubles the ratio of input voltage to output voltage, which is strongly related to its high efficiency. The state of art CMOS-based conventional switched-capacitance charge pump achieve power efficiency as 82% and output as 1.8V with 1.0V input voltage with 130nm technology. The steep-slope and low-threshold HTFET device characteristics are utilized to extend the input voltage range to below 0.20 V. Meanwhile, the uni-directional current conduction is utilized to reduce the reverse energy loss and to simplify the non-overlapping phase controlling. Furthermore, with uni-directional current conduction, an improved cross-coupled charge pump topology is proposed for higher voltage output and power-conversion-efficiency (PCE). Simulation results show that the proposed HTFET charge pump achieves 90.4% and 91.4% power conversion efficiency with a 1.0 kΩ resistive load. The DC results obtained are 0.37 V and 0.57 V, when the input voltage is 0.20 V and 0.30 V, respectively.