Tunnel FET based Field Programmable Gate Arrays

Open Access
Author:
Mukundrajan, Ravindhiran
Graduate Program:
Computer Science and Engineering
Degree:
Master of Science
Document Type:
Master Thesis
Date of Defense:
None
Committee Members:
  • Vijaykrishnan Narayanan, Thesis Advisor
Keywords:
  • Emerging nanotech
  • Tunnel FET
  • FPGA
  • Low Power
Abstract:
The proliferation of mobile computing systems has created a new segment in the semiconductor ecosystem where energy eciency is the most critical design parameter. Moreover, sustaining the growth trajectory of this segment is a dicult task due to lengthy design turnaround times associated with custom design. These difficulties are further exacerbated by the consumer expectation for rapid improvements in functionality within the same energy budget. To cope with these twin challenges, it is critical to explore energy-efficient emerging technologies that can outperform CMOS and construct design frameworks that signi cantly reduce the design turnaround time. Commercially-available CMOS-based FPGAs provide a flexible platform for rapid prototyping and implementation, however they are energy inefficient for utilization in mobile systems. In this thesis, the design of an energy-ecient FPGA based on Tunnel FETs (TFETs), a prospective CMOS replacement device, is presented. Novel circuit designs are showcased to overcome idiosyncracies unique to TFETs, that prevent them from being direct replacements for MOSFETs in FPGAs. The impact of TFET usage at the system level is characterized by simulating a FPGA architecture that demonstrate a signi cant reduction ( 1x) in critical path delay at reduced operating voltages, compared to traditional FinFET based FPGAs at the 22nm node.