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1. Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems

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2. Creating and Probing Molecular Assemblies for Single-Molecule Devices

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3. Exploring Power Reliability Tradeoffs in On-Chip Networks

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4. Redundancy and Parallelism Tradeoffs for Reliable, High-Performance Architectures

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5. Implications of Future Technologies on the Design of FPGAs

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7. RELIABILITY ANALYSIS AND OPTIMIZATION FOR NANOSCALE SYSTEM-ON-CHIP DESIGN

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8. Issues in low-power and reliable wireless commuication system design

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9. Network-on-Chip Architectures: A Holistic Design Exploration

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10. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches

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11. EXPLOITING MULTI-THREADED APPLICATION CHARACTERISTICS TO OPTIMIZE PERFORMANCE AND POWER OF CHIP-MULTIPROCESSORS

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12. Clock Network and Phase-Locked Loop Power Estimation and Experimentation

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14. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS

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16. An Operator-Centric Mission Planning Environment to Reduce Mission Complexity for heterogeneous Unmanned Vehicles

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19. Dependable Sensor Networks

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20. Energy-aware hardware and software optimizations for embedded systems

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21. Sparse Scientific Applications: Improving Performance and Energy Characteristics on Advanced Architectures

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22. System Level Power and Reliability Modeling

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23. The Control, Communication, and Computation Language (C3L): Completing the Design Cycle in Complex Distributed System Development

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24. PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT

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25. HIGH-PERFORMANCE SIGNAL PROCESSING ON RECONFIGURABLE PLATFORMS

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26. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications

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27. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY

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28. A Configurable Platform for Sensor and Image Processing

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29. CO-ADAPTING SCIENTIFIC APPLICATIONS AND ARCHITECTURES TOWARD ENERGY-EFFICIENT HIGH PERFORMANCE COMPUTING

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30. Quality of Service Provisioning in Clusters

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31. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS

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33. Secure Communications in Sensor Networks

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34. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS

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35. Addressing Reliability Issues in Performance-Critical Processor Structures

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36. COMPILER DIRECTED MEMORY HIERARCHY DESIGN AND MANAGEMENT IN CHIP MULTIPROCESSORS

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37. A Reliable Design Flow for Platform FPGAs.

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38. Analysis of Failures in Nanoscale Devices

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39. SOFT ERRORS IN LOGIC CIRCUITS: ANALYSIS AND MODELING

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40. Influence of Emerging Technologies on Interconnect Architectures

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41. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors

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42. Software Based Techniques for Robust Computing on Chip Multiprocessors

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45. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management

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46. Communication and Scheduling in Clusters : A User-Level Perspective

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47. Power Management of Enterprise Storage Systems

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48. CLOSING THE GAP BETWEEN FPGAs AND ASICs: THE APPLICATIONS OF CLOCK SKEW SCHEDULING ON FPGAs

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49. EMBEDDED HARDWARE FACE DETECTION FOR DIGITAL SURVEILLANCE SYSTEMS

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