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1. Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems

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2. Design and Analysis of Heterogeneous Networks for Chip-Multiprocessors

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3. A GPU based implementation of Center Surround Distribution Distance Algorithm for Feature Recognition

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4. Exploring Power Reliability Tradeoffs in On-Chip Networks

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6. Redundancy and Parallelism Tradeoffs for Reliable, High-Performance Architectures

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7. Implications of Future Technologies on the Design of FPGAs

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8. RELIABILITY ANALYSIS AND OPTIMIZATION FOR NANOSCALE SYSTEM-ON-CHIP DESIGN

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9. Issues in low-power and reliable wireless commuication system design

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10. Network-on-Chip Architectures: A Holistic Design Exploration

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11. SOFT ERROR RATE SIMULATION AND INITIAL DESIGN CONSIDERATIONS OF NEUTRON INTERCEPTING SILICON CHIP (NISC)

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12. FAULT TOLERANT SIGNAL PROCESSING FOR VLSI CIRCUITS

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13. Clock Network and Phase-Locked Loop Power Estimation and Experimentation

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15. Design of High-Performance, Energy-Efficient, and Reliable Network-on-Chip (NoC) Architectures

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16. Sensor Network Interoperability and Reconfiguration through Mobile Agents

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17. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS

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20. EXPLORING THE MEMORY HIERARCHY DESIGN WITH EMERGING MEMORY TECHNOLOGIES

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