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41. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity

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Open Access

42. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System

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Open Access

43. system-on-chip integration of heterogeneous accelerators for perceptual computing

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Open Access

44. A Study of DRAM Optimization to Break the Memory Wall

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Open Access

45. Rethinking the memory hierarchy design with nonvolatile memory technologies

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Open Access

46. Configurable Accelerators for Visual and Text Analytics

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Open Access

47. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory

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Open Access

48. design methodologies of three-dimensional integrated circuits (3D ICs)

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Open Access

49. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline

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Open Access

50. Architecting Byte-addressable Non-volatile Memories for Main Memory

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Open Access