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Start Over Degree PHD Committee Member Mary Jane Irwin Committee Member Kenneth Jenkins Committee Member William Evan Higgins Keyword low power VLSI design

1. Clock Network and Phase-Locked Loop Power Estimation and Experimentation

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Open Access
Author:
Duarte, David Enrique
Title:
Clock Network and Phase-Locked Loop Power Estimation and Experimentation
Graduate Program:
Electrical Engineering
Keywords:
CPU clock energy modeling
power estimation
PLL design
low power VLSI design
File:
Download thesis.pdf
Committee Members:
William Evan Higgins, Committee Member
Kenneth Jenkins, Committee Chair/Co-Chair
Mary Jane Irwin, Committee Chair/Co-Chair
Vijaykrishnan Narayanan, Committee Member
Thomas Nelson Jackson, Committee Member

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