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1. Towards Minimizing the Adverse Effects of Temperature on High Performance Digital Systems

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2. Creating and Probing Molecular Assemblies for Single-Molecule Devices

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3. Exploring Power Reliability Tradeoffs in On-Chip Networks

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4. Redundancy and Parallelism Tradeoffs for Reliable, High-Performance Architectures

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5. Implications of Future Technologies on the Design of FPGAs

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6. RELIABILITY ANALYSIS AND OPTIMIZATION FOR NANOSCALE SYSTEM-ON-CHIP DESIGN

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7. Issues in low-power and reliable wireless commuication system design

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8. Network-on-Chip Architectures: A Holistic Design Exploration

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9. Minimizing End-To-End Interference in I/O Stacks Spanning Shared Multi-Level Buffer Caches

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10. EXPLOITING MULTI-THREADED APPLICATION CHARACTERISTICS TO OPTIMIZE PERFORMANCE AND POWER OF CHIP-MULTIPROCESSORS

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11. Clock Network and Phase-Locked Loop Power Estimation and Experimentation

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13. DEEP SUBMICRON (DSM) DESIGN AUTOMATION TECHNIQUES TO MITIGATE PROCESS VARIATIONS

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15. An Operator-Centric Mission Planning Environment to Reduce Mission Complexity for heterogeneous Unmanned Vehicles

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18. Dependable Sensor Networks

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19. Energy-aware hardware and software optimizations for embedded systems

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20. Sparse Scientific Applications: Improving Performance and Energy Characteristics on Advanced Architectures

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21. System Level Power and Reliability Modeling

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22. The Control, Communication, and Computation Language (C3L): Completing the Design Cycle in Complex Distributed System Development

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23. PROGRAM ALLOCATION AND IMPLEMENTATION OF CACHE IN A DATAFLOW ENVIRONMENT

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24. HIGH-PERFORMANCE SIGNAL PROCESSING ON RECONFIGURABLE PLATFORMS

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25. A TIQ Based CMOS Flash A/D Converter for System-on-Chip Applications

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26. ORCHESTRATING THE COMPILER AND MICROARCHITECTURE FOR REDUCING CACHE ENERGY

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27. A Configurable Platform for Sensor and Image Processing

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28. CO-ADAPTING SCIENTIFIC APPLICATIONS AND ARCHITECTURES TOWARD ENERGY-EFFICIENT HIGH PERFORMANCE COMPUTING

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29. Quality of Service Provisioning in Clusters

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30. DESIGNING ENERGY-EFFICIENT AND RELIABLE CACHES AND INTERCONNECTS

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32. Secure Communications in Sensor Networks

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33. CONFIGURABLE ACCELERATORS FOR VIDEO ANALYTICS

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34. Addressing Reliability Issues in Performance-Critical Processor Structures

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35. COMPILER DIRECTED MEMORY HIERARCHY DESIGN AND MANAGEMENT IN CHIP MULTIPROCESSORS

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36. A Reliable Design Flow for Platform FPGAs.

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37. Analysis of Failures in Nanoscale Devices

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38. SOFT ERRORS IN LOGIC CIRCUITS: ANALYSIS AND MODELING

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39. Influence of Emerging Technologies on Interconnect Architectures

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40. Dynamic Shared Resource Management for Providing Predictable Performance in Multicore Processors

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41. Software Based Techniques for Robust Computing on Chip Multiprocessors

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44. Reducing Interference in Memory Hierarchy Resources Using Application Aware Management

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45. Communication and Scheduling in Clusters : A User-Level Perspective

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46. Power Management of Enterprise Storage Systems

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47. CLOSING THE GAP BETWEEN FPGAs AND ASICs: THE APPLICATIONS OF CLOCK SKEW SCHEDULING ON FPGAs

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48. EMBEDDED HARDWARE FACE DETECTION FOR DIGITAL SURVEILLANCE SYSTEMS

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50. DEVICE AND ARCHITECTURE CO-DESIGN FOR ULTRA-LOW POWER LOGIC USING EMERGING TUNNELING-BASED DEVICES

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52. ARCHITECTURAL LEVEL POWER ESTIMATION AND EXPERIMENTATION

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54. Design Exploration for Three-dimensional Integrated Circuits (3DICs)

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55. Modeling and Leveraging Emerging Non-Volatile Memories for Future Computer Designs

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56. Dynamic Resource Management for Energy-efficiency and Quality-of-Service in Chip Multiprocessors

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57. CACHE-AWARE APPLICATION PARALLELIZATION AND OPTIMIZATION FOR MULTICORES

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58. SCHEDULING AND RESOURCE MANAGEMENT FOR NEXT GENERATION CLUSTERS

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60. Shared Storage Resource Management to Provide predictable Performance

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61. Accelerating Cortical Processing for Real Time Neuromorphic Vision Systems

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62. Algorithmic Approaches for Enhancing Speedup, Energy and Resiliency Measures of Sparse Scientific Computations

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63. Sub-50 nm Multi-Segment Interconnect Design: A treatise on Speed, Reliability and Signal Integrity

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64. Compiler-based Memory Optimizations for High Performance Computing Systems

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65. Compiler Optimizations for SIMD/GPU/Multicore Architectures

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66. Modeling and Architecting Emerging Non-volatile Resistive Random Access Memory for Future Computer System

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67. system-on-chip integration of heterogeneous accelerators for perceptual computing

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68. Parallel I/o Profiling and Optimization in Hpc Systems

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69. A Study of DRAM Optimization to Break the Memory Wall

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70. Rethinking the memory hierarchy design with nonvolatile memory technologies

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72. Configurable Accelerators for Visual and Text Analytics

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73. Architecture-level Designs using Emerging Non-volatile Memories

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74. Modeling, Circuit Design, and Microarchitectural Optimization of Emerging Resistive Memory

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75. design methodologies of three-dimensional integrated circuits (3D ICs)

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76. Enabling Intelligent Vision Systems in a Configurable Multi-algorithm Pipeline

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77. Architecting Byte-addressable Non-volatile Memories for Main Memory

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78. Three Dimensional Integrated Circuit Design and Test

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79. EXPLOITING AND ACCOMMODATING ASYMMETRIES IN MEMORY TO ENABLE EFFICIENT MULTI-CORE SYSTEMS

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80. DIGITAL/MIXED-SIGNAL CIRCUIT DESIGNS WITH STEEP SLOPE III-V TUNNEL TRANSISTORS

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81. Enabling New Computation Paradigms with Emerging Technologies

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82. HARDWARE SOFTWARE CO-DESIGN FOR OPTIMIZING MEMORY HIERARCHY IN MANY-CORE AND MULTI-SOCKET SYSTEMS

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