A platform for evaluating embedded multi-core systems

Open Access
Madineedi, Komala Subhadra
Graduate Program:
Electrical Engineering
Master of Science
Document Type:
Master Thesis
Date of Defense:
June 27, 2016
Committee Members:
  • Vijaykrishnan Narayanan, Thesis Advisor
  • Sumeet Kumar Gupta, Committee Member
  • Kultegin Aydin, Committee Member
  • Heterogeneous multi-core systems
  • Coherent Accelerator Processor Interface (CAPI)
  • OpenRISC cores
Multiprocessor system on chip (MPSoC) such as the POWER8 processor is a heterogeneous multi- core architecture. These multi-core architectures contain a host processor and smaller cores, which act like general purpose programmable accelerators, performing the computation. The host processor runs the main application and offloads the parallelizable (computation- and data- intensive) parts to the multiple cores for execution. In this thesis, a platform for evaluating such embedded multi-core systems is provided. The work integrated a low power processing platform that uses an accelerator that generates non-streaming memory access patterns with the Coherent Accelerator Processor Interface for the Power8 system, in order to perform characterization of workloads on the system to explore the benefits of CAPI features. The design with the integrated framework is synthesized as part of the work. It also delves into PageRank algorithm and explains one of the many ways to parallelize the algorithm in the context of the accelerator design.