Electronic Design Automation Challenges in Three Dimensional Integrated Chips (3D ICs)

Open Access
Falkenstern, Paul
Graduate Program:
Computer Science and Engineering
Master of Science
Document Type:
Master Thesis
Date of Defense:
November 11, 2008
Committee Members:
  • Dr Yuan Xie, Thesis Advisor
  • Yuan Xie, Thesis Advisor
  • OpenAccess
  • Scan Chains
  • Three Dimensional Integrated Chips (3D ICs)
  • Floorplan
  • Power/Ground Network Synthesis
Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing two-dimensional (2D) chip designs. Today's integrated chips face several problems, such as global interconnect scaling and bandwidth limitations. By stacking multiple device layers, 3D ICs can overcome these issues and produce chips with higher performance, less power consumption, smaller footprints and mixed-technology capabilities. However, there are several challenges in the development of 3D ICs. First, the current 3D Electronic Design Automation (EDA) tools still do not offer enough support to effectively design 3D IC for widespread production. Also, there is a lack of testing and verification tools and methods to ensure the correct functionality of 3D ICs. In addition, integrating existing 3D EDA tools may be challenging because of the differences between the tools. Because of the early development of 3D ICs and the challenge of constructing a design flow, the design space of 3D ICs have not fully been explored. These issues need to be solved before 3D ICs are developed into a viable commercial product. This thesis helps address these EDA challenges in 3D ICs by exploring three areas in 3D IC development: 3D IC scan chain ordering methods, modeling 3D ICs in OpenAccess, and 3D IC Floorplan and Power/Ground (P/G) Co-synthesis. The tools and methods developed in these areas will further the understanding of the properties, benefits and limitations of 3D ICs. To facilitate the testing of 3D ICs, three 3D scan chain ordering methods are developed: VIA3D, MAP3D and OPT3D. VIA3D and MAP3D require no changes to a 2D ordering algorithm. In addition, VIA3D has the lowest possible number of TSVs in the scan chain, while MAP3D results in the most number of TSVs among the methods. However, OPT3D results in the best scan chain wirelength, with improvements over 2D wirelength of 36.3\% for 2 tiers, 48.6\% for 3 tiers and 53.4\% for 3 tiers. These 3D scan chain ordering methods can be used to construct 3D scan chains, which will permit the testing of 3D ICs. A 3D OA model is developed to provide interoperability between 3D EDA tools. The model consists of a 2D database containing 2D tier designs and 3D database containing TSV designs and a 3D design which aggregates the design information from the 2D tiers. In addition, a tool which creates a 3D technology for the 3D database is created. The centralized 3D design database will allow for the creation of tightly integrated design flows to efficiently design 3D ICs. A 3D IC Floorplan and P/G Co-synthesis tool is developed to design the 3D P/G network. By using this tool, a floorplan can be generated with consideration of the IR drops in the circuit, which leads to better performing devices. In addition, the co-synthesis tool can be used to explore the 3D P/G design space for a design. Two topologies were studied in this work: a uniform mesh where each tier has the same pitch; and a non-uniform mesh where each tier may have a different pitch. The results of experiments using the 3D Floorplan and P/G Co-synthesis tool can show the effects of 3D ICs on P/G networks and can be used to compare the different topologies. The results show that as the number of tiers increase in a 3D IC, the P/G routing area also increases due to the construction of P/G meshes on each tier. In addition, as the number of tiers increase, the IR drop decreases due to the shortened P/G wires and the distribution of the P/G network throughout the tiers. For 2 tiers, each type of mesh has approximately a 35\% increase of P/G area and a 22\% decrease in IR drop. For 3 tiers, the IR drop decreases by approximately 30\% for both meshes, and the P/G area increases by 63\% for uniform meshes and by 92\% for non-uniform meshes. For 4 tiers, the P/G area increases by approximately 100\%, or 2X, and the IR drop decreases by 33\%. An increased P/G routing area increases the routing congestion in the chip, but a decreased IR drop leads to faster and more reliable performance. The main difference between the uniform mesh and non-uniform mesh is that the non-uniform mesh has a better improvement in the average IR drop in the circuits. This may be caused by the ability of the different pitches on each tier to more effectively deliver power to the modules. The other difference between the two topologies is the P/G area for 3 tiers, where the non-uniform mesh has a larger P/G area. However, for the P/G area for 2 and 4 tiers and for the maximum IR drop of the circuit, both topologies have similar results. Therefore, though non-uniform mesh may be slightly more efficient in reducing the average IR drop, both types of meshes have similar advantages and disadvantages. The 3D Floorplan and P/G Co-synthesis considers the IR drop during floorplanning, explores the 3D P/G design space, and evaluates 3D IC's effect on 3D P/G networks. This allows a more efficiently designed P/G network, improving the performance of the entire design. Though there is still a significant amount of work to be done before 3D ICs become commercially feasible, the tools and methods developed and presented in this thesis help solve these issues. They can be used to enhance the maturation of 3D ICs. As 3D ICs develop into a practical technology, computers and systems will be able to utilize the benefits, leading to improved products for the user.