Study of Thin Silicon Oxides and High-K Materials for Gate Dielectrics in Metal-Insulator-Si Structures

Open Access
Jiang, Jiayu
Graduate Program:
Engineering Science and Mechanics
Doctor of Philosophy
Document Type:
Date of Defense:
June 18, 2004
Committee Members:
  • Osama O Awadelkarim, Committee Chair
  • S Ashok, Committee Member
  • Mark William Horn, Committee Member
  • Jerzy Ruzyllo, Committee Member
  • Christopher Roman Wronski, Committee Member
  • thin oxide
  • high k
  • gate dielectrics
  • characterization
The development of a gate stack system (dielectric, electrode, and their compatibility with plasma etching processes and the scaled complementary metal oxide semiconductor [CMOS] integrated circuit [IC] process flow) presents major materials and processing challenges as IC industry approaches the sub-100 nm technology generation by the year 2006 and beyond. The continually shrinking gate-oxide thickness, necessitated by the requirement of higher gate capacitances for high drive current, results in direct tunneling and excessive leakage currents in metal-oxide-Si field-effect transistors (MOSFETs). To obtain high gate capacitance and inhibit tunneling, relatively thick insulators of high dielectric constants (high-k) are needed in place of gate oxides in MOSFETs. The research in this thesis will cover a series of issues related to the scaling of submicron devices. In the first part of this thesis we examined the plasma-process induced damages in thin-gate oxide MOSFETs and its identification and characterization through electrical measurements. We found that, with the aggressive shrinking of oxide thickness around and below 50Å, conventional transistor parameter measurements such as threshold voltage (Vth), transconductance (Gm) and subthreshold swing (S) failed to resolve differences in devices with variable degree of plasma-process induced damage. We demonstrated that in these thin-oxide MOSFETs the gate leakage current (Ig) is the only transistor parameter which can detect plasma-processing induced changes in oxide charge and interface states. These results are interpreted in terms of the strong dependence of Ig on trap-assisted tunneling which dominates conduction in oxides within the studied thickness regime. In subsequent studies, thin-gate oxide MOS capacitors and MOSFETs were subjected to Fowler-Nordheim (FN) stress and Hot-Carrier (HC) stress, respectively, and tested with deep level transient spectroscopy (DLTS) to monitor trap generation during plasma process as well as during device operation. Charge states in SiO2 and Si/ SiO2 interface states were observed under different FN stress temperatures and their causes were attributed to carrier injection during the stress. For the first time bulk Si defects are reported to be generated by FN stressing on thin gate oxides which raises a serious concern of carrier mobility in channel region of corresponding MOSFETs. During HC stress, we found that HC stress in thin-oxide transistors promotes interface damage while oxide charge trapping becomes less significant. The observed degradation is no longer localized near the drain side. In the second part of the thesis, we focus our studies on the electrical properties of high-k gate stack systems. Different high-k dielectrics, SrTa2O6, ZrSiO4, ZrO2 and HfO2 prepared by liquid source misted chemical deposition, and TiO2 prepared by chemical vapor deposition were used as the insulators in metal-insulator-Si (MIS) capacitors which were examined using CV/IV and DLTS. It is revealed, for the first time, that the accumulation capacitance of the MIS with the high-k dielectric is strongly dependent on the measuring temperature and frequency. The capacitance dependence on temperature in the MIS with the high-k dielectric is seen to proceed in an opposite direction to that of MOS capacitors while the capacitance dependence on frequency in the MIS is significantly larger than that of MOS capacitors. An equivalent circuit model is proposed and the discrepancy is explained by the impedance contributions from a thin and low quality interfacial layer, between the high-k dielectric and the Si substrate, often inadvertently incorporated during the high-k dielectric growth. These observations call for efforts to be put towards the careful evaluation and possible elimination of this low-quality interfacial layer from gate dielectric stacks.