A Comprehensive Study of Thermal-Aware Data Placement in 3D DRAMs: The Role of Data Convection and GPU Integration
Open Access
- Author:
- Khadirsharbiyani, Soheil
- Graduate Program:
- Computer Science and Engineering (MS)
- Degree:
- Master of Science
- Document Type:
- Master Thesis
- Date of Defense:
- November 01, 2023
- Committee Members:
- Mahmut Taylan Kandemir, Thesis Advisor/Co-Advisor
John Morgan Sampson, Committee Member
Chitaranjan Das, Program Head/Chair - Keywords:
- 3D Integrated Circuits
Temperature Optimization
Temperature Modelling
3D DRAM
Graphics processors
Data Placement
Thermal Issues - Abstract:
- Over the past decade, there has been a growing fascination with the potential of stacked DRAMs to enhance the computing capabilities of various systems. Particularly in high-performance computing (HPC) environments, these stacked DRAMs offer a valuable asset in the form of substantial bandwidth. However, despite the extensive research efforts dedicated to exploring 3D stacked DRAM-based designs, a significant challenge remains largely unaddressed - the inherent limitation in memory capacity associated with stacked DRAMs. In the context of this thesis, we embark on a comprehensive exploration, meticulously examining the integration of stacked DRAM in a 3D configuration atop a GPU. This type of integration, when combined with 2.5D stacked DRAM, amplifies both capacity and bandwidth without increasing the package size, which is beneficial to the insatiable memory demands of emerging applications such as deep learning. Our investigations are rooted in rigorous experiments conducted using a cycle-level simulator, demonstrating the thermal challenges that accompany this vertical 3D integration. Notably, we discern that the heat generated by the GPU significantly impacts the retention times of the 3D stacked DRAM layers, with proximity to the GPU being a critical factor. This phenomenon necessitates selective and frequent refresh cycles for certain sections of DRAM, giving rise to thermal-induced Non-Uniform Memory Access (NUMA) paradigms. In response to these thermal constraints, this thesis introduces and empirically assesses an innovative concept known as "Data Convection" in three distinct forms: Intra-layer, Inter-layer, and Intra + Inter-layer. These strategies prioritize the strategic placement of frequently accessed data, ensuring it is orchestrated in a thermally-conscious manner to preserve retention. In doing so, they harness both bank-level and channel-level parallelism. Our evaluations, conducted using a cycle-level GPU simulator, underscore the effectiveness of these proposed methods. Specifically, in multi-application scenarios, the Intra-layer, Inter-layer, and Intra + Inter-layer strategies enhance performance by 1.8\%, 11.7\%, and 14.4\%, respectively, compared to a baseline model incorporating 3D + 2.5D stacked DRAMs without any data placement. This research not only deepens our comprehension of the intricate relationship between stacked DRAMs and GPUs but also lays the foundation for future "thermally-efficient" memory architectures.