A Study of Parallelism-locality Tradeoffs across Memory Hierarchy
Open Access
- Author:
- Yedlapalli, Praveen
- Graduate Program:
- Computer Science and Engineering
- Degree:
- Doctor of Philosophy
- Document Type:
- Dissertation
- Date of Defense:
- May 21, 2015
- Committee Members:
- Mahmut Taylan Kandemir, Dissertation Advisor/Co-Advisor
Mahmut Taylan Kandemir, Committee Chair/Co-Chair
Padma Raghavan, Committee Member
Chitaranjan Das, Committee Member
Dinghao Wu, Committee Member - Keywords:
- Memory
SOC
parallelism
locality - Abstract:
- As the number of cores on a chip increases, the memory bandwidth requirements become a scalability issue. Current CMPs incorporate multiple resources both on-chip and on-chip to handle these bandwidth requirements. There are multiple ways to organize these resources (caches and memory) with different parallelism and locality tradeoffs. In this dissertation, we first study parallelism vs. locality tradeoffs in each layer of the memory hierarchy, as well as the cross-layer interactions. Using the observations from the characterization study we proposed a dynamic memory migration technique which optimizes both parallelism and locality metrics in the memory subsystem and thereby improve performance. Then we study the challenges faced by traditional cache prefetchers in modern CMPs and identify the major pitfalls in their use in these new systems. We show how memory prefetching can take advantage of the memory locality and prefetch opportunistically, leading to better effciency than traditional cache prefetchers. We explore the emerging area of mobile computing and identify mobile memory bandwidth requirement as a major challenge faced in these systems. We propose a novel solution of breaking the application frames into smaller ones to exploit the memory locality and reduce the memory bandwidth requirements significantly in such systems.