Improving Performance of In-memory Key-value Stores Using a 3d-stacked Architecture

Open Access
Stalev, Ivan Dimitrov
Graduate Program:
Computer Science and Engineering
Master of Science
Document Type:
Master Thesis
Date of Defense:
June 22, 2015
Committee Members:
  • John Morgan Sampson, Thesis Advisor
  • Mary Jane Irwin, Thesis Advisor
  • Key-value store
  • DRAM cache
  • architecture
Web services and cloud computing are rapidly growing as more users get online around the world and utilize the internet for a growing number of purposes. This puts more demand on in-memory key-value stores as web servers must handle a massive influx of user requests. Data centers will thus find it more challenging to meet their SLAs (Service Level Agreements), as the latency of the 90th percentile of requests may become quite unpredictable. To alleviate this growing concern, we utilize a stacked DRAM architecture as a LLC (last-level cache) that is modified to exploit some common power-law access patterns in user requests. More specifically, we observe that the majority of the memory traffic generated by a key-value store is due to requests for large values, even though large values account for a very small portion (typically around 5%) of overall requests. Thus, we choose to prioritize the cachelines that belong to large values in the stacked DRAM cache by allowing priority cachelines to only be evicted by other priority cachelines. Using this priority scheme, we are able to improve the 90th percentile request latency by as much as 42.4% over a standard stacked DRAM cache architecture.