Double-Gate, Tri-Layer, and Vertical ZnO TFTs and Circuits

Open Access
Sun, Kaige
Graduate Program:
Electrical Engineering
Doctor of Philosophy
Document Type:
Date of Defense:
June 12, 2015
Committee Members:
  • Thomas Nelson Jackson, Dissertation Advisor
  • Thomas Nelson Jackson, Committee Chair
  • Suman Datta, Committee Member
  • Noel Christopher Giebink, Committee Member
  • Kyusun Choi, Committee Member
  • double-gate TFT
  • tri-layer TFT
  • vertical TFT
  • zinc oxide
  • circuits
  • modeling
  • digital and analog circuits
  • rectifier
Zinc oxide thin film transistor (ZnO TFT) technology can be applied to the integrated circuits (ICs) of high-performance large-area electronics. In this dissertation, innovations in device structure, fabrication process, and circuitry are made to overcome the original limitations of the technology and to improve the performance of ZnO TFTs and their circuits. The contents include research on double-gate TFTs, tri-layer TFTs, double-gate tri-layer TFTs, selective etching of Al2O3 over ZnO, and TFT-based digital/analog circuits. Additionally, self-aligned vertical ZnO TFTs for low-cost device scaling are studied with physics-based modeling. ZnO TFTs with the active layers deposited by a plasma enhanced atomic layer deposition (PEALD) system are used as the baseline devices in this research. These devices are n-channel TFTs of high mobility >10 cm2/Vs, large on-off ratio >107, and negative turn-on voltage. Due to the lack of stable p-channel TFTs, NMOS-only circuitry is one choice for ZnO TFT-based circuits. A double-gate ZnO TFT structure is developed, which allows tuning of the turn-on voltage of the TFTs by biasing the top gate electrode. Characterization circuits in enhancement-depletion mode with high gain >100 and large noise margin are achieved with double-gate TFTs. Digital circuits including logic gates, full adders, flip-flops, and frequency dividers and the corresponding design method are developed. A low-power low-input-voltage active rectifier as an analog circuit are also customized and realized. The research lays the foundation for using double-gate ZnO TFTs to build complex digital/analog electronic systems on a large scale. To obtain a more positive turn-on voltage, which reduces the static power consumption of TFT circuits, tri-layer ZnO TFT and double-gate tri-layer ZnO TFT structures with in-situ PEALD Al2O3 passivation are developed. Selective etching of the Al2O3 passivation layer without hurting the ZnO active layer for metal contacts is accomplished with pH-controlled selective etchants, which is the critical process to realize these structures and is developed with in-depth study. Alkaline aqueous solutions with pH between about 9 and 12 are found to etch Al2O3 at a useful rate with minimal attack of ZnO. High selectivity >400:1 and an Al2O3 etch rate of ∼50 nm/min are obtained using a pH 12 etch solution at 60 °C. Near-zero turn-on voltage and improved bias-stress stability are obtained with the tri-layer structure due to the in-situ protected back surface of the ZnO channel layers. Vertical TFTs (VTFTs) with ZnO channel layers deposited with spatial ALD (SALD) are studied, which achieves sub-micrometer channel length and increased drive current using only low-resolution patterning. A physics-based model is developed using the Synopsys Sentaurus drift-diffusion simulator. Acceptor-like traps above and below the conduction band minimum are needed to model the semiconductor behavior of SALD ZnO. By producing the asymmetric I–V characteristics with simulations, the role of the ungated ZnO region near the foot of the VTFT is understood, which has a more significant effect on charge injection than on charge extraction. Good agreement with experimental characteristics is obtained in modeling VTFTs with different ungated region lengths.