Physics, Fabrication And Characterization Of Iii-v Multi-gate Fets For Low Power Electronics

Open Access
Author:
Thathachary, Arun V
Graduate Program:
Electrical Engineering
Degree:
Doctor of Philosophy
Document Type:
Dissertation
Date of Defense:
July 13, 2015
Committee Members:
  • Suman Datta, Dissertation Advisor
  • Theresa Stellwag Mayer, Committee Member
  • Weihua Guan, Committee Member
  • Nitin Samarth, Committee Member
  • Kultegin Aydin, Committee Member
  • Roman Engel Herbert, Committee Member
Keywords:
  • III-V
  • low power
  • CMOS
  • FinFET
  • transport
  • MOSFET
  • Hall mobility
  • transconductance
  • injection velocity
Abstract:
With transistor technology close to its limits for power constrained scaling and the simultaneous emergence of mobile devices as the dominant driver for new scaling, a pathway to significant reduction in transistor operating voltage to 0.5V or lower is urgently sought. This however implies a fundamental paradigm shift away from mature Silicon technology. III-V compound semiconductors hold great promise in this regard due to their vastly superior electron transport properties making them prime candidates to replace Silicon in the n-channel transistor. Among the plethora of binary and ternary compounds available in the III-V space, InxGa1-xAs alloys have attracted significant interest due to their excellent electron mobility, ideally placed bandgap and mature growth technology. Simultaneously, electrostatic control mandates multi-gate transistor designs such as the FinFET at extremely scaled nodes. This dissertation describes the experimental realization of III-V FinFETs incorporating InXGa1-XAs heterostructure channels for high performance, low power logic applications. The chapters that follow present experimental demonstrations, simulations and analysis on the following aspects (a) motivation and key figures of merit driving material selection and design; (b) dielectric integration schemes for high-k metal-gate stack (HKMG) realization on InXGa1-XAs, including surface clean and passivation techniques developed for high quality interfaces; (c) novel techniques for transport (mobility) characterization in nanoscale multi-gate FET architectures with experimental demonstration on In0.7Ga0.3As nanowires; (d) Indium composition and quantum confined channel design for InXGa1-XAs FinFETs and (e) InAs heterostructure designs for high performance FinFETs. Each chapter also contains detailed benchmarking of results against state of the art demonstrations in Silicon and III-V material systems. The dissertation concludes by assessing the feasibility of InXGa1-XAs FinFET devices as n-channel Silicon replacement for low power logic technology scaling.